公开(公告)号：US20140264545A1

公开(公告)日：2014-09-18

申请号：US13891238

申请日：2013-05-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ching-Hung Wang ,  Jyun-Siang Huang ,  Chien-Hung Liu ,  Chia-Wen Cheng ,  Ying-Tso Chen

IPC: H01L27/115

CPC classification number: H01L21/28282 ,  H01L21/76802 ,  H01L27/11568

Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.

Abstract translation: 提供了一种半导体元件及其制造方法。 半导体元件包括衬底，多个掺杂条，存储材料层，多个导电镶嵌结构和电介质结构。 在衬底中形成掺杂条。 存储材料层形成在衬底上，并且存储材料层包括位于掺杂条的两侧的存储区。 导电镶嵌结构形成在记忆材料层上。 介电结构形成在掺杂条上和导电镶嵌结构之间。 导电镶嵌结构在垂直于掺杂条延伸的方向的方向上延伸。

公开(公告)号：US09312139B2

公开(公告)日：2016-04-12

申请号：US13891238

申请日：2013-05-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ching-Hung Wang ,  Jyun-Siang Huang ,  Chien-Hung Liu ,  Chia-Wen Cheng ,  Ying-Tso Chen

IPC: H01L21/28 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L21/76802 ,  H01L27/11568

Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.

Abstract translation: 提供了一种半导体元件及其制造方法。 半导体元件包括衬底，多个掺杂条，存储材料层，多个导电镶嵌结构和电介质结构。 在衬底中形成掺杂条。 存储材料层形成在衬底上，并且存储材料层包括位于掺杂条的两侧的存储区。 导电镶嵌结构形成在记忆材料层上。 介电结构形成在掺杂条上和导电镶嵌结构之间。 导电镶嵌结构在垂直于掺杂条延伸的方向的方向上延伸。

公开(公告)号：US08969202B2

公开(公告)日：2015-03-03

申请号：US14174931

申请日：2014-02-07

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

IPC: H01L21/44 ,  H01L21/8234 ,  H01L21/302 ,  H01L21/461 ,  H01L21/283 ,  H01L27/105 ,  H01L21/28 ,  H01L29/49 ,  H01L27/118

CPC classification number: H01L21/283 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/823443 ,  H01L27/1052 ,  H01L29/4933

Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

Abstract translation: 以下公开了金属硅化物的制造方法。 提供具有第一区域和第二区域的衬底。 在衬底上形成硅层。 进行平面化处理以使硅层具有平坦表面。 去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。 第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。 覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。 金属硅化物形成在第一栅极和第二栅极的顶表面上。

公开(公告)号：US20140154881A1

公开(公告)日：2014-06-05

申请号：US14174931

申请日：2014-02-07

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

IPC: H01L21/283

CPC classification number: H01L21/283 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/823443 ,  H01L27/1052 ,  H01L29/4933

Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

Abstract translation: 以下公开了金属硅化物的制造方法。 提供具有第一区域和第二区域的衬底。 在衬底上形成硅层。 进行平面化处理以使硅层具有平坦表面。 去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。 第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。 覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。 金属硅化物形成在第一栅极和第二栅极的顶表面上。