公开(公告)号：US20150325668A1

公开(公告)日：2015-11-12

申请号：US14272133

申请日：2014-05-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Chi-Sheng Peng ,  Chia-Wen Cheng

IPC: H01L29/49 ,  H01L21/3205 ,  H01L21/285 ,  H01L29/66 ,  H01L21/321 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/311

CPC classification number: H01L29/4933 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/32105 ,  H01L21/3211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/78

Abstract: Provided is a method for fabricating a semiconductor device including the following steps. A silicon-containing conductive layer is formed on a substrate. Then, a dielectric layer is formed around the silicon-containing conductive layer. A portion of the dielectric layer is removed to expose a first sidewall of the silicon-containing conductive layer. A shielding structure is formed on a partial surface of the silicon-containing conductive layer, and the shielding structure exposes at least the first sidewall. A metal layer is formed on the substrate to cover the silicon-containing conductive layer not covered by the shielding structure. A salicide process is performed to form a silicide layer.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 在基板上形成含硅导电层。 然后，在含硅导电层周围形成电介质层。 去除介电层的一部分以暴露含硅导电层的第一侧壁。 屏蔽结构形成在含硅导电层的局部表面上，屏蔽结构至少露出第一侧壁。 在基板上形成金属层以覆盖未被屏蔽结构覆盖的含硅导电层。 进行自对准硅化物工艺以形成硅化物层。

公开(公告)号：US20140264545A1

公开(公告)日：2014-09-18

申请号：US13891238

申请日：2013-05-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ching-Hung Wang ,  Jyun-Siang Huang ,  Chien-Hung Liu ,  Chia-Wen Cheng ,  Ying-Tso Chen

IPC: H01L27/115

CPC classification number: H01L21/28282 ,  H01L21/76802 ,  H01L27/11568

Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.

Abstract translation: 提供了一种半导体元件及其制造方法。 半导体元件包括衬底，多个掺杂条，存储材料层，多个导电镶嵌结构和电介质结构。 在衬底中形成掺杂条。 存储材料层形成在衬底上，并且存储材料层包括位于掺杂条的两侧的存储区。 导电镶嵌结构形成在记忆材料层上。 介电结构形成在掺杂条上和导电镶嵌结构之间。 导电镶嵌结构在垂直于掺杂条延伸的方向的方向上延伸。

公开(公告)号：US20160189999A1

公开(公告)日：2016-06-30

申请号：US14582918

申请日：2014-12-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Chia-Wen Cheng

IPC: H01L21/764 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/115 ,  H01L21/285

CPC classification number: H01L21/764 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157

Abstract: Provided is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a plurality of stacked structures and a dielectric layer. The stacked structures are disposed on a substrate. The dielectric layer is disposed on the substrate, and covers the stacked structures. An air gap is located between two adjacent stacked structures, and a top end of the air gap is higher than a top end of each of the stacked structures.

Abstract translation: 提供一种半导体器件及其制造方法。 半导体器件包括多个堆叠结构和介电层。 层叠结构设置在基板上。 电介质层设置在基板上并覆盖堆叠结构。 气隙位于两个相邻的堆叠结构之间，气隙的顶端高于每个堆叠结构的顶端。

公开(公告)号：US09312139B2

公开(公告)日：2016-04-12

申请号：US13891238

申请日：2013-05-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ching-Hung Wang ,  Jyun-Siang Huang ,  Chien-Hung Liu ,  Chia-Wen Cheng ,  Ying-Tso Chen

IPC: H01L21/28 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L21/76802 ,  H01L27/11568

Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.

Abstract translation: 提供了一种半导体元件及其制造方法。 半导体元件包括衬底，多个掺杂条，存储材料层，多个导电镶嵌结构和电介质结构。 在衬底中形成掺杂条。 存储材料层形成在衬底上，并且存储材料层包括位于掺杂条的两侧的存储区。 导电镶嵌结构形成在记忆材料层上。 介电结构形成在掺杂条上和导电镶嵌结构之间。 导电镶嵌结构在垂直于掺杂条延伸的方向的方向上延伸。

公开(公告)号：US09166016B1

公开(公告)日：2015-10-20

申请号：US14272133

申请日：2014-05-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Chi-Sheng Peng ,  Chia-Wen Cheng

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/311 ,  H01L21/321 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/4933 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/32105 ,  H01L21/3211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/78

Abstract: Provided is a method for fabricating a semiconductor device including the following steps. A silicon-containing conductive layer is formed on a substrate. Then, a dielectric layer is formed around the silicon-containing conductive layer. A portion of the dielectric layer is removed to expose a first sidewall of the silicon-containing conductive layer. A shielding structure is formed on a partial surface of the silicon-containing conductive layer, and the shielding structure exposes at least the first sidewall. A metal layer is formed on the substrate to cover the silicon-containing conductive layer not covered by the shielding structure. A salicide process is performed to form a silicide layer.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 在基板上形成含硅导电层。 然后，在含硅导电层周围形成电介质层。 去除介电层的一部分以暴露含硅导电层的第一侧壁。 屏蔽结构形成在含硅导电层的局部表面上，屏蔽结构至少露出第一侧壁。 在基板上形成金属层以覆盖未被屏蔽结构覆盖的含硅导电层。 进行自对准硅化物工艺以形成硅化物层。