公开(公告)号：US10388664B2

公开(公告)日：2019-08-20

申请号：US15913190

申请日：2018-03-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yukai Huang ,  Chun Ling Chiang ,  Yung-Tai Hung ,  Chun Min Cheng ,  Tuung Luoh ,  Ling Wuu Yang ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/00

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

公开(公告)号：US20180269222A1

公开(公告)日：2018-09-20

申请号：US15462201

申请日：2017-03-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yukai Huang ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L27/11582 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L27/11582 ,  H01L21/32133 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive interface layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive interface layer.

公开(公告)号：US20180337140A1

公开(公告)日：2018-11-22

申请号：US15602019

申请日：2017-05-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tuung Luoh ,  Yung-Tai Hung ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L23/00 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/58

Abstract: An integrated circuit includes a stack in a stack region and a region outside the stack region. A buttress structure disposed outside the stack includes a fence-shaped, electrically passive element configured to oppose expansion of materials outside the stack region in a direction toward the stack region.

公开(公告)号：US20250089258A1

公开(公告)日：2025-03-13

申请号：US18465166

申请日：2023-09-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Meng-Hsun Hsieh ,  Tuung Luoh ,  Kuang-Wei Chen ,  Kuang-Chao Chen ,  Ta-Hung Yang

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

Abstract: A manufacturing method of a memory device may be applied to a three-dimensional NAND memory device with high capacity and high performance. In a manufacturing process of the three-dimensional NAND memory device, a material of a control gate (word line) is tungsten. The forming method of a tungsten layer includes nucleation and bulk formation performed. In at least one of the nucleation and the bulk formation, hydrogen flow is between 1000 and 20000 sccm. At least one time of soak with nitrogen may also be performed after the nucleation. A tungsten grain size in the tungsten layer is 70 nm or more.

公开(公告)号：US20250105017A1

公开(公告)日：2025-03-27

申请号：US18471294

申请日：2023-09-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsun-Wei Chang ,  Kuang-Wei Chen ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L21/3105 ,  H01L21/762 ,  H10B43/35

Abstract: A method of manufacturing a memory device at least includes the following steps. A first interconnect and a first dielectric layer are formed on a substrate. A first chemical mechanical polishing process is performed on the first dielectric layer. A stack structure is formed over the first dielectric layer and a staircase structure is formed in the stack structure. A second dielectric layer is formed on the substrate to cover the stack structure and the staircase structure. A second chemical mechanical polishing process is performed on the second dielectric layer. A depth of second grooves of a second polishing pad used in the second chemical mechanical polishing process is smaller than a depth of first grooves of a first polishing pad used in the first chemical mechanical polishing process. The memory device may be a 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US20200273868A1

公开(公告)日：2020-08-27

申请号：US16287910

申请日：2019-02-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chi-Min Chen ,  Yung-Tai Hung ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L27/11521 ,  G11C8/14

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

公开(公告)号：US10892265B2

公开(公告)日：2021-01-12

申请号：US16287910

申请日：2019-02-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chi-Min Chen ,  Yung-Tai Hung ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L27/11521 ,  G11C8/14

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

公开(公告)号：US20170076976A1

公开(公告)日：2017-03-16

申请号：US14855815

申请日：2015-09-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Tsan Yeh ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76232 ,  H01L29/0649

Abstract: An isolation structure and a method of fabricating the same are provided. The isolation structure includes a buffer layer and an encapsulation layer. The buffer layer is located in a trench of a substrate. The encapsulation layer is located in the trench and encapsulates around the buffer layer, wherein the buffer layer is unexposed and is not in contacted with the trench. A material of the buffer layer is different from a material of the encapsulation layer.

Abstract translation: 提供隔离结构及其制造方法。 隔离结构包括缓冲层和封装层。 缓冲层位于衬底的沟槽中。 封装层位于沟槽中并封装在缓冲层周围，其中缓冲层未曝光并且不与沟槽接触。 缓冲层的材料与封装层的材料不同。

公开(公告)号：US09236219B2

公开(公告)日：2016-01-12

申请号：US13886631

申请日：2013-05-03

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Chung Chen ,  Shin-Chang Tsai ,  Ta-Hung Yang

IPC: H01J37/26

CPC classification number: H01J37/26 ,  G01B15/08 ,  G01B2210/56 ,  H01J37/28 ,  H01J2237/2814 ,  H01J2237/2817 ,  H01L22/12

Abstract: Measurements of line roughness are separated into groups depending upon pre-layers. Image data collected from similar pre-layer types are considered together in order to separate effects of line roughness from distortion of measurements caused by the pre-layers. The resulting line roughness measurements are used to estimate an aspect of line quality.

Abstract translation: 线粗糙度的测量根据预层分为几组。 从相似的预先图层类型收集的图像数据被一起考虑，以便分离线粗糙度与由预层引起的测量失真的影响。 所得线粗糙度测量用于估计线质量的一个方面。