公开(公告)号：US20180337140A1

公开(公告)日：2018-11-22

申请号：US15602019

申请日：2017-05-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tuung Luoh ,  Yung-Tai Hung ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L23/00 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/58

Abstract: An integrated circuit includes a stack in a stack region and a region outside the stack region. A buttress structure disposed outside the stack includes a fence-shaped, electrically passive element configured to oppose expansion of materials outside the stack region in a direction toward the stack region.

公开(公告)号：US20160110859A1

公开(公告)日：2016-04-21

申请号：US14516961

申请日：2014-10-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Hsiao-Leng Li ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06T7/00

CPC classification number: G06T7/001 ,  G06T7/12 ,  G06T2207/10056 ,  G06T2207/30148

Abstract: An inspection method for contact by die to database is provided. In the method, a plurality of raw images of contacts in a wafer is obtained, and a plurality of locations of the raw images is then recoded to obtain a graphic file. After that, the graphic file is aligned on a design database of the chip. An image extraction is then performed on the raw images to obtain a plurality of image contours of the contacts. Thereafter, a difference in critical dimension between the image contours of the contacts and corresponding contacts in the design database are measured in order to obtain the inspection result for contacts in the wafer.

Abstract translation: 提供了一种用于与数据库接触的检查方法。 在该方法中，获得晶片中的接触的多个原始图像，然后重新编码原始图像的多个位置以获得图形文件。 之后，图形文件在芯片的设计数据库上对齐。 然后对原始图像执行图像提取以获得联系人的多个图像轮廓。 此后，为了获得晶片中的触点的检查结果，测量了触点的图像轮廓与设计数据库中的对应触点之间的临界尺寸差异。

公开(公告)号：US09006003B1

公开(公告)日：2015-04-14

申请号：US14220993

申请日：2014-03-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Chi-Min Chen ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: H01L21/00 ,  G11C99/00 ,  H01L21/66 ,  G01R31/28

CPC classification number: H01L22/14 ,  G01R31/2851 ,  G06T7/0004 ,  G06T2207/10061 ,  G06T2207/30148 ,  G11C29/006 ,  G11C29/56008 ,  G11C2029/5604

Abstract: A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in each of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a bitmap failure detection is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted into a plurality of physical locations, and the physical locations are overlapped with the physical coordinates so as to rapidly obtain correlations between the failure bits and the defects.

Abstract translation: 提供了一种检测与物理坐标相关联的位图故障的方法。 在该方法中，首先获得晶片映射检查的数据，并且数据包括晶片内的每个层中的缺陷图像和缺陷的多个物理坐标。 此后，执行位图故障检测以获得晶片内的故障位的数字坐标。 数字坐标被转换成多个物理位置，并且物理位置与物理坐标重叠，以便快速获得故障位与缺陷之间的相关性。

公开(公告)号：US10388664B2

公开(公告)日：2019-08-20

申请号：US15913190

申请日：2018-03-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yukai Huang ,  Chun Ling Chiang ,  Yung-Tai Hung ,  Chun Min Cheng ,  Tuung Luoh ,  Ling Wuu Yang ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/00

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

公开(公告)号：US20180269222A1

公开(公告)日：2018-09-20

申请号：US15462201

申请日：2017-03-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yukai Huang ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L27/11582 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L27/11582 ,  H01L21/32133 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive interface layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive interface layer.

公开(公告)号：US20160351493A1

公开(公告)日：2016-12-01

申请号：US14723076

申请日：2015-05-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chien-Lan Chiu ,  Yung-Tai Hung ,  Chin-Ta Su ,  Tuung Luoh

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5329

Abstract: A semiconductor device is provided, which includes a first conductive layer disposed on a substrate, a dielectric layer with at least an opening disposed on the first conductive layer, and a plurality of plugs filling up the openings. At least a portion of the dielectric layer adjacent to the openings is Si-rich, and each of the plugs includes a second conductive layer surrounded by a barrier layer.

Abstract translation: 提供一种半导体器件，其包括设置在基板上的第一导电层，至少设置在第一导电层上的开口的电介质层和填充开口的多个插塞。 与开口相邻的电介质层的至少一部分是富Si的，并且每个插塞包括被阻挡层包围的第二导电层。

公开(公告)号：US20250105017A1

公开(公告)日：2025-03-27

申请号：US18471294

申请日：2023-09-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsun-Wei Chang ,  Kuang-Wei Chen ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L21/3105 ,  H01L21/762 ,  H10B43/35

Abstract: A method of manufacturing a memory device at least includes the following steps. A first interconnect and a first dielectric layer are formed on a substrate. A first chemical mechanical polishing process is performed on the first dielectric layer. A stack structure is formed over the first dielectric layer and a staircase structure is formed in the stack structure. A second dielectric layer is formed on the substrate to cover the stack structure and the staircase structure. A second chemical mechanical polishing process is performed on the second dielectric layer. A depth of second grooves of a second polishing pad used in the second chemical mechanical polishing process is smaller than a depth of first grooves of a first polishing pad used in the first chemical mechanical polishing process. The memory device may be a 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US20200273868A1

公开(公告)日：2020-08-27

申请号：US16287910

申请日：2019-02-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chi-Min Chen ,  Yung-Tai Hung ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L27/11521 ,  G11C8/14

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

公开(公告)号：US09869712B2

公开(公告)日：2018-01-16

申请号：US14694017

申请日：2015-04-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  I-Jen Huang ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06F17/50 ,  G01R31/28 ,  G01R31/265

CPC classification number: G01R31/2831 ,  G01R31/2653

Abstract: A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.

公开(公告)号：US09244112B2

公开(公告)日：2016-01-26

申请号：US14275437

申请日：2014-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsiang-Chou Liao ,  Tuung Luoh ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: H01L21/66 ,  G01R31/04 ,  H01J37/22 ,  H01J37/244 ,  H01J37/28 ,  G01R31/305

CPC classification number: G01R31/04 ,  G01R31/305 ,  H01J37/222 ,  H01J37/244 ,  H01J37/28 ,  H01J2237/049 ,  H01J2237/063 ,  H01J2237/221 ,  H01J2237/24592 ,  H01J2237/2594 ,  H01J2237/28 ,  H01J2237/2817 ,  H01L22/12 ,  H01L22/14

Abstract: A method for detecting an electrical defect of contact/via plugs is provided. In the method, the contact/via plugs are monitored by an electron-beam (E-Beam) inspection tool to capture an image with a VC (voltage contrast) difference, and then an image extraction is performed on the image with the VC difference, wherein the image extraction is based on Target gray level/back ground gray level. The extracted image is contrasted with a layout design base to obtain a blind contact or Quasi-blind issue of contact/via plugs. A grayscale value of the VC difference having the blind contact or Quasi-blind issue is compared with a determined range of grayscale value to determine whether the VC difference is abnormal.

Abstract translation: 提供一种用于检测接触/通孔的电气缺陷的方法。 在该方法中，通过电子束（E-Beam）检查工具来监视接触/通孔塞以捕获具有VC（电压对比度）差异的图像，然后对具有VC差异的图像执行图像提取 ，其中所述图像提取基于目标灰度/背景灰度级。 提取的图像与布局设计基础形成对照，以获得接触/通孔插头的盲接或准盲问题。 将具有盲接或准盲问题的VC差的灰阶值与确定的灰度值范围进行比较，以确定VC差异是否异常。