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    Method of fabricating deep trench semiconductor devices, and deep trench semiconductor devices
    4.
    发明授权
    Method of fabricating deep trench semiconductor devices, and deep trench semiconductor devices 有权
    制造深沟槽半导体器件的方法以及深沟槽半导体器件

    公开(公告)号：US09349746B1

    公开(公告)日：2016-05-24

    申请号：US14594768

    申请日：2015-01-12

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ta-Hone Yang ,  Nan-Tsu Lian ,  An Chyi Wei ,  Sheng-Yuan Chang ,  Kuang-Chao Chen

    IPC: H01L29/51 ,  H01L27/115 ,  H01L21/768 ,  H01L21/28

    CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/511 ,  H01L29/518

    Abstract: Present example embodiments relate generally to methods for fabricating semiconductor devices comprising forming an initial stack of alternating insulative and conductive layers over a substrate, identifying a plurality of bit line locations and word line locations for the initial stack, including a first bit line location and a first word line location, and forming, from the initial stack, a vertical arrangement of bit lines in the first bit line location, the vertical arrangement of bit lines having opposing sidewalls. The method further comprises forming a word line by forming a thin conductive layer over selected sections of the opposing sidewalls, the selected sections of the opposing sidewalls being sections within the first word line location. The forming the word line further comprises depositing conductive material adjacent to each thin conductive layer, the deposited conductive material in direct contact with the thin conductive layer.

    Abstract translation: 本示例实施例一般涉及用于制造半导体器件的方法，包括在衬底上形成交替的绝缘和导电层的初始叠层，识别用于初始堆叠的多个位线位置和字线位置，包括第一位线位置和 第一字线位置，并且从初始堆叠形成第一位线位置中的位线的垂直布置，位线的垂直布置具有相对的侧壁。 该方法还包括通过在相对侧壁的选定部分上形成薄导电层来形成字线，相对侧壁的选定部分是第一字线位置内的部分。 形成字线还包括沉积与每个薄导电层相邻的导电材料，沉积的导电材料与薄导电层直接接触。

    METHOD FOR FABRICATING MEMORY DEVICE
    6.
    发明申请
    METHOD FOR FABRICATING MEMORY DEVICE 有权

    公开(公告)号：US20220077187A1

    公开(公告)日：2022-03-10

    申请号：US17528068

    申请日：2021-11-16

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Yao-An Chung ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

    IPC: H01L27/11582 ,  H01L23/48 ,  H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311

    Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

    INSPECTION METHOD FOR CONTACT BY DIE TO DATABASE
    8.
    发明申请
    INSPECTION METHOD FOR CONTACT BY DIE TO DATABASE 审中-公开
    DIE到DATABASE联系的检查方法

    公开(公告)号：US20160110859A1

    公开(公告)日：2016-04-21

    申请号：US14516961

    申请日：2014-10-17

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Tuung Luoh ,  Hsiao-Leng Li ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

    IPC: G06T7/00

    CPC classification number: G06T7/001 ,  G06T7/12 ,  G06T2207/10056 ,  G06T2207/30148

    Abstract: An inspection method for contact by die to database is provided. In the method, a plurality of raw images of contacts in a wafer is obtained, and a plurality of locations of the raw images is then recoded to obtain a graphic file. After that, the graphic file is aligned on a design database of the chip. An image extraction is then performed on the raw images to obtain a plurality of image contours of the contacts. Thereafter, a difference in critical dimension between the image contours of the contacts and corresponding contacts in the design database are measured in order to obtain the inspection result for contacts in the wafer.

    Abstract translation: 提供了一种用于与数据库接触的检查方法。 在该方法中，获得晶片中的接触的多个原始图像，然后重新编码原始图像的多个位置以获得图形文件。 之后，图形文件在芯片的设计数据库上对齐。 然后对原始图像执行图像提取以获得联系人的多个图像轮廓。 此后，为了获得晶片中的触点的检查结果，测量了触点的图像轮廓与设计数据库中的对应触点之间的临界尺寸差异。

    Method of detecting bitmap failure associated with physical coordinate
    9.
    发明授权
    Method of detecting bitmap failure associated with physical coordinate 有权
    检测与物理坐标相关的位图故障的方法

    公开(公告)号：US09006003B1

    公开(公告)日：2015-04-14

    申请号：US14220993

    申请日：2014-03-20

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Tuung Luoh ,  Chi-Min Chen ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

    IPC: H01L21/00 ,  G11C99/00 ,  H01L21/66 ,  G01R31/28

    CPC classification number: H01L22/14 ,  G01R31/2851 ,  G06T7/0004 ,  G06T2207/10061 ,  G06T2207/30148 ,  G11C29/006 ,  G11C29/56008 ,  G11C2029/5604

    Abstract: A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in each of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a bitmap failure detection is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted into a plurality of physical locations, and the physical locations are overlapped with the physical coordinates so as to rapidly obtain correlations between the failure bits and the defects.

    Abstract translation: 提供了一种检测与物理坐标相关联的位图故障的方法。 在该方法中，首先获得晶片映射检查的数据，并且数据包括晶片内的每个层中的缺陷图像和缺陷的多个物理坐标。 此后，执行位图故障检测以获得晶片内的故障位的数字坐标。 数字坐标被转换成多个物理位置，并且物理位置与物理坐标重叠，以便快速获得故障位与缺陷之间的相关性。

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