公开(公告)号：US10388664B2

公开(公告)日：2019-08-20

申请号：US15913190

申请日：2018-03-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yukai Huang ,  Chun Ling Chiang ,  Yung-Tai Hung ,  Chun Min Cheng ,  Tuung Luoh ,  Ling Wuu Yang ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/00

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

公开(公告)号：US20160351493A1

公开(公告)日：2016-12-01

申请号：US14723076

申请日：2015-05-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chien-Lan Chiu ,  Yung-Tai Hung ,  Chin-Ta Su ,  Tuung Luoh

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5329

Abstract: A semiconductor device is provided, which includes a first conductive layer disposed on a substrate, a dielectric layer with at least an opening disposed on the first conductive layer, and a plurality of plugs filling up the openings. At least a portion of the dielectric layer adjacent to the openings is Si-rich, and each of the plugs includes a second conductive layer surrounded by a barrier layer.

Abstract translation: 提供一种半导体器件，其包括设置在基板上的第一导电层，至少设置在第一导电层上的开口的电介质层和填充开口的多个插塞。 与开口相邻的电介质层的至少一部分是富Si的，并且每个插塞包括被阻挡层包围的第二导电层。

公开(公告)号：US09252102B2

公开(公告)日：2016-02-02

申请号：US14297679

申请日：2014-06-06

Applicant: Macronix International Co., Ltd.

Inventor： Bing-Lung Yu ,  Chin-Tsan Yeh ,  Yung-Tai Hung ,  Chin-Ta Su

IPC: H01L23/52 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a conductive layer, a via, and a barrier layer disposed between the conductive layer and the via. The barrier layer is stuffed with oxygen.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括导电层，通孔和设置在导电层和通孔之间的阻挡层。 阻挡层充满氧气。

公开(公告)号：US20150357286A1

公开(公告)日：2015-12-10

申请号：US14297679

申请日：2014-06-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Bing-Lung Yu ,  Chin-Tsan Yeh ,  Yung-Tai Hung ,  Chin-Ta Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a conductive layer, a via, and a barrier layer disposed between the conductive layer and the via. The barrier layer is stuffed with oxygen.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括导电层，通孔和设置在导电层和通孔之间的阻挡层。 阻挡层充满氧气。

公开(公告)号：US10892265B2

公开(公告)日：2021-01-12

申请号：US16287910

申请日：2019-02-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chi-Min Chen ,  Yung-Tai Hung ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L27/11521 ,  G11C8/14

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

公开(公告)号：US09070634B1

公开(公告)日：2015-06-30

申请号：US14141391

申请日：2013-12-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Chien-Lan Chiu ,  Yung-Tai Hung ,  Chin-Ta Su

IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L21/31055 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/31155

Abstract: A method of fabricating a semiconductor device is provided. A substrate is provided. Thereafter, a dielectric layer is formed on the substrate, wherein the dielectric layer includes a first portion adjacent to the substrate and a second portion adjacent to the first portion. Afterwards, the dielectric layer is treated with nitrogen trifluoride (NF3) to remove the second portion of the dielectric layer and therefore expose the first portion of the dielectric layer. A semiconductor device is also provided.

Abstract translation: 提供一种制造半导体器件的方法。 提供基板。 此后，在基板上形成电介质层，其中介电层包括与基板相邻的第一部分和与第一部分相邻的第二部分。 之后，用三氟化氮（NF 3）处理电介质层以去除电介质层的第二部分，从而暴露电介质层的第一部分。 还提供了半导体器件。

公开(公告)号：US20200273868A1

公开(公告)日：2020-08-27

申请号：US16287910

申请日：2019-02-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chi-Min Chen ,  Yung-Tai Hung ,  Tuung Luoh ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L27/11521 ,  G11C8/14

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

公开(公告)号：US20180337140A1

公开(公告)日：2018-11-22

申请号：US15602019

申请日：2017-05-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tuung Luoh ,  Yung-Tai Hung ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L23/00 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/58

Abstract: An integrated circuit includes a stack in a stack region and a region outside the stack region. A buttress structure disposed outside the stack includes a fence-shaped, electrically passive element configured to oppose expansion of materials outside the stack region in a direction toward the stack region.

公开(公告)号：US09685373B2

公开(公告)日：2017-06-20

申请号：US14793029

申请日：2015-07-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Meng-Tsung Ko ,  Yung-Tai Hung ,  Chin-Ta Su

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76883 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/535

Abstract: A method of forming a conductive plug is disclosed. A material layer having at least one opening is provided on a substrate. A first conductive layer is deposited in the opening, wherein the first conductive layer does not completely fill up the opening. A second conductive layer is deposited on the first conductive layer. A surface treatment is performed after the step of depositing the first conductive layer and before the step of depositing the second conductive layer, so that the first deposition rate of the second conductive layer at the lower portion of the opening is greater the second deposition rate of the second conductive layer at the upper portion of the opening. A void-free conductive plug can be easily formed with the method of the invention.

公开(公告)号：US20170011960A1

公开(公告)日：2017-01-12

申请号：US14793029

申请日：2015-07-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Meng-Tsung Ko ,  Yung-Tai Hung ,  Chin-Ta Su

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76883 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/535

Abstract: A method of forming a conductive plug is disclosed. A material layer having at least one opening is provided on a substrate. A first conductive layer is deposited in the opening, wherein the first conductive layer does not completely fill up the opening. A second conductive layer is deposited on the first conductive layer. A surface treatment is performed after the step of depositing the first conductive layer and before the step of depositing the second conductive layer, so that the first deposition rate of the second conductive layer at the lower portion of the opening is greater the second deposition rate of the second conductive layer at the upper portion of the opening. A void-free conductive plug can be easily formed with the method of the invention.

Abstract translation: 公开了一种形成导电插塞的方法。 具有至少一个开口的材料层设置在基板上。 第一导电层沉积在开口中，其中第一导电层不完全填满开口。 第二导电层沉积在第一导电层上。 在沉积第一导电层的步骤之后和沉积第二导电层的步骤之前进行表面处理，使得开口下部的第二导电层的第一沉积速率大于第二导电层的第二沉积速率 在开口的上部的第二导电层。 通过本发明的方法可以容易地形成无孔的导电塞。