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    Process for localized repair of graphene-coated lamination stacks and printed circuit boards
    2.
    发明授权
    Process for localized repair of graphene-coated lamination stacks and printed circuit boards 有权

    公开(公告)号：US12289839B2

    公开(公告)日：2025-04-29

    申请号：US17305233

    申请日：2021-07-01

    Applicant: Mellanox Technologies, Ltd. ,  Bar-Ilan University

    Inventor： Elad Mentovich ,  Boaz Atias ,  Doron Naveh ,  Eilam Zigi Ben Smolinsky ,  Adi Levi

    IPC: H05K3/22 ,  C01B32/188 ,  H05K1/02

    Abstract: Processes for localized lasering of a lamination stack and graphene-coated printed circuit board (PCB) are disclosed. An example PCB may include a lamination stack, post-lamination, that may further include a core, an adhesive layer, and at least one graphene-metal structure. A top layer of graphene of the graphene-metal structure may have never been grown before the lamination process or may have been removed post-lamination such that a portion of the top layer of graphene is missing. The localized lasering process described herein may grow (for the first time) or re-grow the graphene layer of the exposed portion of the metal layer without adverse effects to the rest of the lamination stack or PCB and while promoting a uniform layer of graphene on the top surface. A process of growing graphene through application of molecular layer and a self-assembled monolayer (SAM), are also described herein.

    High-density memory macro
    6.
    发明申请
    High-density memory macro 审中-公开

    公开(公告)号：US20190074040A1

    公开(公告)日：2019-03-07

    申请号：US16121672

    申请日：2018-09-05

    Applicant: Mellanox Technologies, Ltd. ,  Bar-Ilan University

    Inventor： Elad Mentovich ,  Narkis Geuli ,  Robert Giterman ,  Alexander Fish ,  Adam Teman

    IPC: G11C7/10 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/412

    Abstract: A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.

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