公开(公告)号：US11327113B2

公开(公告)日：2022-05-10

申请号：US16525077

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： David D. Wilmoth

IPC: G01R31/317 ,  G06F11/30 ,  G01R31/3185 ,  G11C7/10 ,  G11C29/48 ,  G11C11/401 ,  G11C29/02 ,  G11C5/04 ,  G11C5/00 ,  G11C29/12 ,  G06F9/38 ,  G11C7/22 ,  G11C29/04

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

公开(公告)号：US20190064265A1

公开(公告)日：2019-02-28

申请号：US15693114

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： David D. Wilmoth

IPC: G01R31/317 ,  G06F11/30 ,  G01R31/3185

CPC classification number: G01R31/31716 ,  G01R31/31713 ,  G01R31/31715 ,  G01R31/31726 ,  G01R31/318536 ,  G01R31/318547 ,  G06F9/381 ,  G06F11/3051 ,  G11C7/222

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

公开(公告)号：US10991404B1

公开(公告)日：2021-04-27

申请号：US16793979

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： David D. Wilmoth

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076

Abstract: Devices and methods include transmitting loopback signals for monitoring operation of a plurality of memory devices. In some embodiments, a first memory device may transmit a loopback strobe signal based at least in part on a strobe signal for the first memory device. In certain embodiments, a frequency of the loopback strobe signal is a fraction of the frequency of the strobe signal. In some embodiments, the first memory device may transmit a loopback data signal based at least in part on the strobe signal, wherein a frequency of the loopback strobe signal is the fraction of the frequency of the strobe signal.

公开(公告)号：US10360959B2

公开(公告)日：2019-07-23

申请号：US16137428

申请日：2018-09-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David D. Wilmoth ,  Jason M. Brown

IPC: G11C8/00 ,  G11C8/18 ,  G11C11/4063 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/28 ,  G11C8/10

Abstract: Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.

公开(公告)号：US10176858B1

公开(公告)日：2019-01-08

申请号：US15691394

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David D. Wilmoth ,  Jason M. Brown

IPC: G11C8/06 ,  G11C8/18 ,  G11C11/4063 ,  G11C8/10

Abstract: Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.

公开(公告)号：US20190353706A1

公开(公告)日：2019-11-21

申请号：US16525077

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： David D. Wilmoth

IPC: G01R31/317 ,  G01R31/3185 ,  G06F11/30

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

公开(公告)号：US10393803B2

公开(公告)日：2019-08-27

申请号：US15693114

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： David D. Wilmoth

IPC: G01R31/317 ,  G06F11/30 ,  G01R31/3185 ,  G06F9/38 ,  G11C7/22

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

公开(公告)号：US20190066745A1

公开(公告)日：2019-02-28

申请号：US16137428

申请日：2018-09-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David D. Wilmoth ,  Jason M. Brown

IPC: G11C8/18 ,  G11C11/4063 ,  G11C8/10

CPC classification number: G11C8/18 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C8/10 ,  G11C11/4063 ,  G11C11/4082 ,  G11C11/4093 ,  G11C29/023 ,  G11C29/28 ,  G11C2207/2254

Abstract: Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.