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    INTEGRATED CIRCUIT FABRICATION
    1.
    发明申请
    INTEGRATED CIRCUIT FABRICATION 有权
    集成电路制造

    公开(公告)号：US20150004786A1

    公开(公告)日：2015-01-01

    申请号：US14486890

    申请日：2014-09-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Luan C. Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

    IPC: H01L21/768 ,  H01L21/306 ,  H01L21/308 ,  H01L21/033

    CPC classification number: H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

    Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

    Abstract translation: 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

    Integrated structures, capacitors and methods of forming capacitors
    2.
    发明授权
    Integrated structures, capacitors and methods of forming capacitors 有权

    公开(公告)号：US11087991B2

    公开(公告)日：2021-08-10

    申请号：US16514928

    申请日：2019-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Eric Freeman ,  Paolo Tessariol

    IPC: H01L21/311 ,  H01L49/02 ,  H01L23/522 ,  H01L27/11582

    Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

    Integrated Structures, Capacitors and Methods of Forming Capacitors
    4.
    发明申请
    Integrated Structures, Capacitors and Methods of Forming Capacitors 审中-公开

    公开(公告)号：US20190341266A1

    公开(公告)日：2019-11-07

    申请号：US16514928

    申请日：2019-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Eric Freeman ,  Paolo Tessariol

    IPC: H01L21/311 ,  H01L27/11582 ,  H01L49/02 ,  H01L23/522

    Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

    Integrated Structures, Capacitors and Methods of Forming Capacitors
    5.
    发明申请
    Integrated Structures, Capacitors and Methods of Forming Capacitors 有权

    公开(公告)号：US20210358759A1

    公开(公告)日：2021-11-18

    申请号：US17391345

    申请日：2021-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Eric Freeman ,  Paolo Tessariol

    IPC: H01L21/311 ,  H01L49/02 ,  H01L23/522 ,  H01L27/11582

    Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

    Integrated structures, capacitors and methods of forming capacitors
    6.
    发明授权
    Integrated structures, capacitors and methods of forming capacitors 有权

    公开(公告)号：US10366901B2

    公开(公告)日：2019-07-30

    申请号：US15451090

    申请日：2017-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Eric Freeman ,  Paolo Tessariol

    IPC: H01L21/311 ,  H01L49/02 ,  H01L23/522 ,  H01L27/11582

    Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

    Integrated circuit fabrication
    8.
    发明授权
    Integrated circuit fabrication 有权
    集成电路制造

    公开(公告)号：US08859362B2

    公开(公告)日：2014-10-14

    申请号：US13962208

    申请日：2013-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Luan C. Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

    IPC: H01L21/8242 ,  H01L27/105 ,  H01L23/544 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033

    CPC classification number: H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

    Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

    Abstract translation: 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法定义第一光致抗蚀剂层中的多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

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