STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME
    2.
    发明申请
    STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME 有权
    带有选择门的存储器单元的行,包含这样的行的存储器件及其访问和形成方法

    公开(公告)号:US20130272066A1

    公开(公告)日:2013-10-17

    申请号:US13892353

    申请日:2013-05-13

    Inventor: Zengtao Liu

    Abstract: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

    Abstract translation: 具有字符串选择栅的存储单元串被配置成同时选择性地将字符串的端部耦合到数据线和源极线,提供包含这种字符串的存储器件以及用于访问和形成这种字符串的方法。 例如,公开了利用串行连接的非易失性存储器单元的垂直结构NAND串的非易失性存储器件。 一种这样的串包括两个或多个串联的非易失性存储单元,其中串的每一端与串的另一端共享串选择门。

    Integrated circuit fabrication
    7.
    发明授权
    Integrated circuit fabrication 有权
    集成电路制造

    公开(公告)号:US08859362B2

    公开(公告)日:2014-10-14

    申请号:US13962208

    申请日:2013-08-08

    Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

    Abstract translation: 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法定义第一光致抗蚀剂层中的多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案,而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

    Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same
    9.
    发明授权
    Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same 有权
    具有串选择门的存储单元的串,并入这样的字符串的存储器,以及访问和形成该字符串的方法

    公开(公告)号:US08792280B2

    公开(公告)日:2014-07-29

    申请号:US13892353

    申请日:2013-05-13

    Inventor: Zengtao Liu

    Abstract: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

    Abstract translation: 具有字符串选择栅的存储单元串被配置成同时选择性地将字符串的端部耦合到数据线和源极线,提供包含这种字符串的存储器件以及用于访问和形成这种字符串的方法。 例如,公开了利用串行连接的非易失性存储器单元的垂直结构NAND串的非易失性存储器件。 一种这样的串包括两个或多个串联的非易失性存储单元,其中串的每一端与串的另一端共享串选择门。

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