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    Apparatuses, circuits, and methods for biasing signal lines
    4.
    发明授权
    Apparatuses, circuits, and methods for biasing signal lines 有权
    用于偏置信号线的装置，电路和方法

    公开(公告)号：US09236102B2

    公开(公告)日：2016-01-12

    申请号：US13651093

    申请日：2012-10-12

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

    IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C8/10 ,  G11C7/12

    CPC分类号： G11C7/12 ,  G11C5/141 ,  G11C5/148 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/56

    摘要： Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

    摘要翻译： 公开了用于偏置存储器阵列中的信号线的装置，电路和方法。 在一个这样的示例中，存储器阵列包括耦合到多个存储器单元的信号线，并且被配置为响应于信号线的偏置条件来提供对多个存储器单元的访问。 存储器阵列还包括耦合到信号线的信号线驱动器，信号线驱动器被配置为向信号线提供偏置信号，并且响应于控制信号在偏置信号中提供预加重。 控制信号响应于操作状态。

    SENSING MEMORY CELLS
    5.
    发明申请
    SENSING MEMORY CELLS 有权
    传感记忆细胞

    公开(公告)号：US20140098607A1

    公开(公告)日：2014-04-10

    申请号：US14046640

    申请日：2013-10-04

    申请人： Micron Technology, Inc.

    发明人： Vishal Sarin ,  Jung Sheng Hoei ,  Frankie Roohparvar ,  Giulio-Giuseppe Marotta

    IPC分类号： G11C16/12

    CPC分类号： G11C16/12 ,  G11C7/16 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5642

    摘要： The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.

    摘要翻译： 本公开包括用于操作存储器单元的方法，设备，模块和系统。 一种方法实施例包括将斜波电压施加到存储器单元的控制栅极和模数转换器（ADC）。 上述方法的实施例还包括响应于斜坡电压何时使存储器单元跳闸感测电路至少部分地检测ADC的输出。

    APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES
    8.
    发明申请
    APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES 有权
    用于偏转信号线的装置，电路和方法

    公开(公告)号：US20160118096A1

    公开(公告)日：2016-04-28

    申请号：US14989678

    申请日：2016-01-06

    申请人： Micron Technology, Inc.

    发明人： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

    IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C7/22

    CPC分类号： G11C7/12 ,  G11C5/141 ,  G11C5/148 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/56

    摘要： Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

    摘要翻译： 公开了用于偏置存储器阵列中的信号线的装置，电路和方法。 在一个这样的示例中，存储器阵列包括耦合到多个存储器单元的信号线，并且被配置为响应于信号线的偏置条件来提供对多个存储器单元的访问。 存储器阵列还包括耦合到信号线的信号线驱动器，信号线驱动器被配置为向信号线提供偏置信号，并且响应于控制信号在偏置信号中提供预加重。 控制信号响应于操作状态。