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公开(公告)号：US20200152278A1
公开(公告)日：2020-05-14
申请号：US16745514
申请日：2020-01-17
摘要： Methods of operating a memory, as well as memory configured to perform such method, include applying an intermediate read voltage to a selected access line for a read operation, adding noise to a sensing operation while applying the intermediate read voltage, determining a value indicative of a number of memory cells of a plurality of memory cells connected to the selected access line that are activated in response to applying the intermediate read voltage to the selected access line, and determining a plurality of read voltages for the read operation in response to the value indicative of the number of memory cells of the plurality of memory cells that are activated in response to applying the intermediate read voltage to the selected access line.
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公开(公告)号：US20190057729A1
公开(公告)日：2019-02-21
申请号：US16165732
申请日：2018-10-19
摘要： Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.
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公开(公告)号：US20170154676A1
公开(公告)日：2017-06-01
申请号：US15431364
申请日：2017-02-13
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C7/12 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0083 , G11C2013/0085 , G11C2013/0088 , G11C2213/79
摘要： Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.
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公开(公告)号：US20160118096A1
公开(公告)日：2016-04-28
申请号：US14989678
申请日：2016-01-06
摘要： Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.
摘要翻译： 公开了用于偏置存储器阵列中的信号线的装置，电路和方法。 在一个这样的示例中，存储器阵列包括耦合到多个存储器单元的信号线，并且被配置为响应于信号线的偏置条件来提供对多个存储器单元的访问。 存储器阵列还包括耦合到信号线的信号线驱动器，信号线驱动器被配置为向信号线提供偏置信号，并且响应于控制信号在偏置信号中提供预加重。 控制信号响应于操作状态。
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公开(公告)号：US20220084896A1
公开(公告)日：2022-03-17
申请号：US17534973
申请日：2021-11-24
发明人： Kenneth William Marr , Chiara Cerafogli , Michele Piccardi , Marco-Domenico Tiburzi , Eric Higgins Freeman , Joshua Daniel Tomayer
摘要： A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.
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公开(公告)号：US10573353B2
公开(公告)日：2020-02-25
申请号：US16118691
申请日：2018-08-31
IPC分类号： G11C5/14 , G06F1/3203 , G06F1/3234 , G05F3/16
摘要： Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.
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公开(公告)号：US20190051333A1
公开(公告)日：2019-02-14
申请号：US16118691
申请日：2018-08-31
摘要： Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.
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公开(公告)号：US09916880B2
公开(公告)日：2018-03-13
申请号：US15474353
申请日：2017-03-30
摘要： Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.
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公开(公告)号：US20170206942A1
公开(公告)日：2017-07-20
申请号：US15474353
申请日：2017-03-30
摘要： Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.
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公开(公告)号：US20160371335A1
公开(公告)日：2016-12-22
申请号：US15253965
申请日：2016-09-01
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F17/30 , G11C15/04 , G06F12/0802 , G11C29/50 , G06F7/20
CPC分类号： G06F17/30495 , G06F3/0628 , G06F7/20 , G06F12/0802 , G06F2212/1021 , G06F2212/608 , G11C7/1006 , G11C15/046 , G11C16/0483 , G11C16/06 , G11C29/50004 , G11C29/50016
摘要： Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.
摘要翻译： 用于促进图案匹配并具有存储器单元阵列的存储器件，用于存储关键字的表示的多个键寄存器和多个复用器，多个多路复用器的每个复用器用于从一个或多个多路复用器中选择一个位的表示 多个密钥寄存器的密钥寄存器与存储在存储器单元阵列中的数据进行比较。
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