公开(公告)号：US20220084896A1

公开(公告)日：2022-03-17

申请号：US17534973

申请日：2021-11-24

Applicant: Micron Technology, Inc.

Inventor： Kenneth William Marr ,  Chiara Cerafogli ,  Michele Piccardi ,  Marco-Domenico Tiburzi ,  Eric Higgins Freeman ,  Joshua Daniel Tomayer

IPC: H01L21/66 ,  G01B7/16

Abstract: A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

公开(公告)号：US10573353B2

公开(公告)日：2020-02-25

申请号：US16118691

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Marcerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G06F1/3203 ,  G06F1/3234 ,  G05F3/16

Abstract: Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.

公开(公告)号：US20190051333A1

公开(公告)日：2019-02-14

申请号：US16118691

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Macerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G05F3/16 ,  G06F1/32

Abstract: Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.

公开(公告)号：US09916880B2

公开(公告)日：2018-03-13

申请号：US15474353

申请日：2017-03-30

Applicant: Micron Technology, Inc.

Inventor： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

IPC: G11C7/00 ,  G11C7/12 ,  G11C8/10 ,  G11C5/14 ,  G11C11/56 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/141 ,  G11C5/148 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/56

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

公开(公告)号：US20170206942A1

公开(公告)日：2017-07-20

申请号：US15474353

申请日：2017-03-30

Applicant: Micron Technology, Inc.

Inventor： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

IPC: G11C7/12 ,  G11C7/22 ,  G11C11/56 ,  G11C8/10 ,  G11C5/14

CPC classification number: G11C7/12 ,  G11C5/141 ,  G11C5/148 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/56

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

公开(公告)号：US20160371335A1

公开(公告)日：2016-12-22

申请号：US15253965

申请日：2016-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Giulio G. Marotta ,  Marco-Domenico Tiburzi ,  Tommaso Vali ,  Frankie F. Roohparvar ,  Agostino Macerola

IPC: G06F17/30 ,  G11C15/04 ,  G06F12/0802 ,  G11C29/50 ,  G06F7/20

CPC classification number: G06F17/30495 ,  G06F3/0628 ,  G06F7/20 ,  G06F12/0802 ,  G06F2212/1021 ,  G06F2212/608 ,  G11C7/1006 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/06 ,  G11C29/50004 ,  G11C29/50016

Abstract: Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

Abstract translation: 用于促进图案匹配并具有存储器单元阵列的存储器件，用于存储关键字的表示的多个键寄存器和多个复用器，多个多路复用器的每个复用器用于从一个或多个多路复用器中选择一个位的表示 多个密钥寄存器的密钥寄存器与存储在存储器单元阵列中的数据进行比较。

公开(公告)号：US11715502B2

公开(公告)日：2023-08-01

申请号：US16774182

申请日：2020-01-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Macerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G06F1/3234 ,  G05F3/16 ,  G06F1/3203 ,  G11C16/30 ,  G11C16/04

CPC classification number: G11C5/145 ,  G05F3/16 ,  G06F1/3203 ,  G06F1/3275 ,  G11C5/147 ,  G11C16/30 ,  G11C16/0458 ,  G11C16/0483

Abstract: Charge pumps of integrated circuit devices might include an input configured to receive an internally-generated first voltage level, an output, and a plurality of stages between its input and output. A particular stage might include a voltage isolation device, a voltage driver, and a capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to the voltage isolation device. The voltage driver might be responsive to a clock signal and to a voltage level of the output of the voltage driver to selectively connect the output of the voltage driver to either a first voltage node configured to receive the first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, or a third voltage node configured to receive a third voltage level lower than the second voltage level.

公开(公告)号：US20200152278A1

公开(公告)日：2020-05-14

申请号：US16745514

申请日：2020-01-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Marco-Domenico Tiburzi

IPC: G11C16/34 ,  G11C29/50 ,  G11C7/06 ,  G11C7/14 ,  G11C16/04 ,  G11C11/56 ,  G11C16/28

Abstract: Methods of operating a memory, as well as memory configured to perform such method, include applying an intermediate read voltage to a selected access line for a read operation, adding noise to a sensing operation while applying the intermediate read voltage, determining a value indicative of a number of memory cells of a plurality of memory cells connected to the selected access line that are activated in response to applying the intermediate read voltage to the selected access line, and determining a plurality of read voltages for the read operation in response to the value indicative of the number of memory cells of the plurality of memory cells that are activated in response to applying the intermediate read voltage to the selected access line.

公开(公告)号：US20190057729A1

公开(公告)日：2019-02-21

申请号：US16165732

申请日：2018-10-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

IPC: G11C7/12 ,  G11C11/56 ,  G11C5/14 ,  G11C8/10 ,  G11C7/22 ,  G11C8/08 ,  G11C8/18

CPC classification number: G11C7/12 ,  G11C5/141 ,  G11C5/148 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/56

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

公开(公告)号：US20170154676A1

公开(公告)日：2017-06-01

申请号：US15431364

申请日：2017-02-13

Applicant: Micron Technology, Inc.

Inventor： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C7/12 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/79

Abstract: Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.