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    Distributed compaction of logical states to reduce program time
    1.
    发明授权
    Distributed compaction of logical states to reduce program time 有权

    公开(公告)号：US11488677B2

    公开(公告)日：2022-11-01

    申请号：US17247435

    申请日：2020-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30

    Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
    2.
    发明申请
    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220277795A1

    公开(公告)日：2022-09-01

    申请号：US17745852

    申请日：2022-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

    IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08

    Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.

    Managing sub-block erase operations in a memory sub-system
    3.
    发明授权
    Managing sub-block erase operations in a memory sub-system 有权

    公开(公告)号：US11335412B2

    公开(公告)日：2022-05-17

    申请号：US16991836

    申请日：2020-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

    IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08

    Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.

    DISTRIBUTED COMPACTION OF LOGICAL STATES TO REDUCE PROGRAM TIME
    10.
    发明申请
    DISTRIBUTED COMPACTION OF LOGICAL STATES TO REDUCE PROGRAM TIME 有权

    公开(公告)号：US20230022858A1

    公开(公告)日：2023-01-26

    申请号：US17960252

    申请日：2022-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

    Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

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