MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM

    公开(公告)号:US20240203507A1

    公开(公告)日:2024-06-20

    申请号:US18531100

    申请日:2023-12-06

    CPC classification number: G11C16/102 G11C16/08 G11C29/52

    Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first wordline of a first die of the memory device. The processing device identifies, based on a first predefined value, a second wordline of a second die of the memory device, wherein the first predefined value is a shift in an index value of the first wordline of the first die of the memory device. The processing device further performs a second programming operation on a second set of cells associated with the second wordline of the second die, wherein the second wordline of the second die is associated with a different index value than the first wordline of the first die.

    ERROR DETECTION FOR PROGRAMMING SINGLE LEVEL CELLS

    公开(公告)号:US20240028214A1

    公开(公告)日:2024-01-25

    申请号:US17871804

    申请日:2022-07-22

    Abstract: Methods, systems, and devices for error detection for programming single level cells of a memory system are described. The memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. The memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. The memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.

    MANAGING PROGRAMMING OPERATION SEQUENCE IN A MEMORY SUB-SYSTEM

    公开(公告)号:US20240411449A1

    公开(公告)日:2024-12-12

    申请号:US18646266

    申请日:2024-04-25

    Abstract: A processing device, operatively coupled with a memory device, performs a first sequence of programming operations on a first set of cells addressable by a first wordline of the memory device. The processing device identifies a second wordline of the memory device, wherein a second physical location of the second wordline is in a predefined relationship with a first physical location of the first wordline. The processing device performs a second sequence of programming operations on a second set of cells addressable by the second wordline of the first die, wherein a first order of the first sequence of programming operations is different from a second order of the second sequence of programming operations.

    MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM

    公开(公告)号:US20240231641A1

    公开(公告)日:2024-07-11

    申请号:US18402306

    申请日:2024-01-02

    CPC classification number: G06F3/0619 G06F3/064 G06F3/0679 G06F12/1009

    Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first sub-block of a first die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks. The processing device identifies, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device. The processing device further performs the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.

    ERROR DETECTION FOR PROGRAMMING SINGLE LEVEL CELLS

    公开(公告)号:US20250044953A1

    公开(公告)日:2025-02-06

    申请号:US18797445

    申请日:2024-08-07

    Abstract: Methods, systems, and devices for error detection for programming single level cells of a memory system are described. The memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. The memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. The memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.

    MANAGING ASYNCHRONOUS POWER LOSS IN A MEMORY DEVICE

    公开(公告)号:US20240194279A1

    公开(公告)日:2024-06-13

    申请号:US18524721

    申请日:2023-11-30

    CPC classification number: G11C16/3459 G11C16/102 G11C16/32

    Abstract: A system can include a plurality of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices, to perform operations comprising: determining whether a parameter of a power supply of the volatile memory device satisfies a threshold criterion; responsive to determining that the parameter of the power supply satisfies the threshold criterion, modifying a value of a parameter of a program operation; and programming, using the modified value of the parameter, designated data stored on the volatile memory device to a designated location on the non-volatile memory device.

    MANAGING AN ORDER OF PROGRAMMING OPERATIONS IN A MEMORY SUB-SYSTEM

    公开(公告)号:US20250085863A1

    公开(公告)日:2025-03-13

    申请号:US18779926

    申请日:2024-07-22

    Abstract: A processing device, operatively coupled with a memory device, receives a request to perform a programming operation on a first set of cells addressable by a first wordline of a first die of the memory device. The processing device identifies a programming order associated with the first wordline. The processing device adjusts, based on the programming order, a biasing scheme associated with the first wordline. The processing device further performs, using the programming order and biasing scheme, the programming operation on the first set of cells addressable by the first wordline.

    MEMORY DEVICE HEALTH MONITORING AND DYNAMIC ADJUSTMENT OF DEVICE PARAMETERS

    公开(公告)号:US20240347127A1

    公开(公告)日:2024-10-17

    申请号:US18627984

    申请日:2024-04-05

    CPC classification number: G11C29/52 G11C29/028

    Abstract: A method for monitoring health of a die in a memory device and dynamically adjusting a device parameter. The method includes receiving a request for performing a memory access operation on a first data unit of a memory device, and determining a value of a media state metric of the first data unit. The method further includes modifying a device parameter of the first data unit to form a modified device parameter in response to determining that the value of the media state metric of the first data unit is greater than a predetermined threshold value, and performing, using the modified device parameter, the memory access operation on the first data unit.

Patent Agency Ranking