公开(公告)号：US20030020071A1

公开(公告)日：2003-01-30

申请号：US09911488

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Robert E. Stengel ,  Robert J. Higgins JR.

IPC: H01L031/0256

CPC classification number: H01L27/0605 ,  H01L21/8258 ,  H01L27/0688

Abstract: A semiconductor apparatus for effecting a plurality of functions involving high frequency signals and low frequency signals includes: (a) at least one first circuit section implemented in at least one first semiconductor material; and (b) at least one second circuit section implemented in at least one second semiconductor material. The at least one second semiconductor material exhibits lower noise generating characteristics than the at least one first semiconductor material at the low frequency signals. The at least one first circuit section and the at least one second circuit section are implemented in an integrated circuit construction. Preferably the integrated circuit construction is a monolithic configuration. Preferably the at least one first semiconductor material includes gallium arsenide. Preferably the at least one second semiconductor material includes silicon.

Abstract translation: 用于实现涉及高频信号和低频信号的多个功能的半导体装置包括：（a）至少一个第一电路部分，其实现在至少一个第一半导体材料中; 和（b）在至少一个第二半导体材料中实现的至少一个第二电路部分。 所述至少一个第二半导体材料在所述低频信号下表现出比所述至少一个第一半导体材料更低的噪声产生特性。 所述至少一个第一电路部分和所述至少一个第二电路部分以集成电路结构实现。 优选地，集成电路结构是单片结构。 优选地，至少一个第一半导体材料包括砷化镓。 优选地，至少一个第二半导体材料包括硅。

公开(公告)号：US20030034501A1

公开(公告)日：2003-02-20

申请号：US09930188

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Robert J. Higgins JR.

IPC: H01L029/74

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L27/0605

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The fabrication of on chip high frequency communications devices such as direct conversion and sampling circuits with direct interface to high speed compound semiconductor material in integrated circuits for high speed data acquisition and CCD image sensor interface is disclosed for direct coupling of imaging signals in single chip applications.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 公开了用于高速数据采集和CCD图像传感器接口的集成电路中与高速化合物半导体材料直接接口的直接转换和采样电路的片上高频通信设备的制造，用于在单个芯片应用中直接耦合成像信号 。

公开(公告)号：US20030030119A1

公开(公告)日：2003-02-13

申请号：US09927396

申请日：2001-08-13

Applicant: Motorola, Inc.

Inventor： Robert J. Higgins JR. ,  Robert E. Stengel

IPC: H01L027/14

CPC classification number: H01L21/02521 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02505 ,  H01L27/20 ,  H01L41/0815 ,  H01L41/1873 ,  H01L41/319 ,  H03H9/02566 ,  H03H9/02574

Abstract: High quality layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The use of monocrystalline piezoelectric material as an overlying layer is disclosed to facilitate the fabrication of on-chip high frequency communications devices such as microwave SAW devices with direct interface to high speed semiconductor devices in the integrated circuit.

Abstract translation: 通过形成用于生长单晶层的顺应性衬底，可以将高质量的单晶材料层生长成覆盖在单晶衬底例如大硅晶片上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 公开了使用单晶压电材料作为覆盖层，以促进片上高频通信设备的制造，例如与集成电路中的高速半导体器件具有直接接口的微波SAW器件。

公开(公告)号：US20030025116A1

公开(公告)日：2003-02-06

申请号：US09918801

申请日：2001-08-01

Applicant: MOTOROLA, INC.

Inventor： Robert J. Higgins JR. ,  Barbara Foley Barenburg ,  Joseph P. Heck ,  Jonathan F. Gorrell

IPC: H01L029/04

CPC classification number: H01L29/66863 ,  G02B6/12002 ,  G02B6/12004 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/31691 ,  H01L21/78 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0688 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/0261 ,  H01S2301/173 ,  H01L2224/80001

Abstract: A semiconductor laminate configured for dividing into predetermined parts has a lateral expanse and includes: (a) a monocrystalline substrate substantially coterminous with the lateral expanse; (b) at least one layer including a monocrystalline compound semiconductor material; and (c) at least one intermediate layer substantially separating the substrate and the compound semiconductor material. The at least one compound semiconductor material layer is arrayed to present intervals substantially devoid of the monocrystalline compound semiconductor material that generally establish lateral limits of the predetermined parts. The method includes the steps of: (a) providing a monocrystalline substrate; (b) providing at least one layer including a monocrystalline compound semiconductor material; (c) providing at least one intermediate layer separating the substrate and the compound semiconductor material; and (d) arraying the compound semiconductor material to present intervals substantially devoid of the compound semiconductor material that generally establish lateral limits of the predetermined parts.

Abstract translation: 被配置为分成预定部分的半导体层压体具有侧向宽度，并且包括：（a）与侧向宽度大致相邻的单晶基板; （b）至少一层包括单晶化合物半导体材料; 和（c）至少一个基本上分离基板和化合物半导体材料的中间层。 排列至少一个化合物半导体材料层以呈现基本上不含单一化合物半导体材料的间隔，其通常建立预定部分的横向极限。 该方法包括以下步骤：（a）提供单晶衬底; （b）提供包含单晶化合物半导体材料的至少一层; （c）提供分离衬底和化合物半导体材料的至少一个中间层; 和（d）将化合物半导体材料排列成基本上不含通常建立预定部分的横向极限的化合物半导体材料的间隔。