公开(公告)号：US20030034535A1

公开(公告)日：2003-02-20

申请号：US09929020

申请日：2001-08-15

Applicant: MOTOROLA, INC.

Inventor： Barbara Foley Barenburg ,  Jonathan F. Gorrell ,  Kenneth D. Cornett

IPC: H01L029/82

CPC classification number: H03H9/2463 ,  B81C1/00246 ,  B81C2203/0735 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L27/20 ,  H01L41/0815 ,  H01L41/094 ,  H01L41/1873 ,  H01L41/319 ,  H03H3/0073

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。

公开(公告)号：US20030025116A1

公开(公告)日：2003-02-06

申请号：US09918801

申请日：2001-08-01

Applicant: MOTOROLA, INC.

Inventor： Robert J. Higgins JR. ,  Barbara Foley Barenburg ,  Joseph P. Heck ,  Jonathan F. Gorrell

IPC: H01L029/04

CPC classification number: H01L29/66863 ,  G02B6/12002 ,  G02B6/12004 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/31691 ,  H01L21/78 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0688 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/0261 ,  H01S2301/173 ,  H01L2224/80001

Abstract: A semiconductor laminate configured for dividing into predetermined parts has a lateral expanse and includes: (a) a monocrystalline substrate substantially coterminous with the lateral expanse; (b) at least one layer including a monocrystalline compound semiconductor material; and (c) at least one intermediate layer substantially separating the substrate and the compound semiconductor material. The at least one compound semiconductor material layer is arrayed to present intervals substantially devoid of the monocrystalline compound semiconductor material that generally establish lateral limits of the predetermined parts. The method includes the steps of: (a) providing a monocrystalline substrate; (b) providing at least one layer including a monocrystalline compound semiconductor material; (c) providing at least one intermediate layer separating the substrate and the compound semiconductor material; and (d) arraying the compound semiconductor material to present intervals substantially devoid of the compound semiconductor material that generally establish lateral limits of the predetermined parts.

Abstract translation: 被配置为分成预定部分的半导体层压体具有侧向宽度，并且包括：（a）与侧向宽度大致相邻的单晶基板; （b）至少一层包括单晶化合物半导体材料; 和（c）至少一个基本上分离基板和化合物半导体材料的中间层。 排列至少一个化合物半导体材料层以呈现基本上不含单一化合物半导体材料的间隔，其通常建立预定部分的横向极限。 该方法包括以下步骤：（a）提供单晶衬底; （b）提供包含单晶化合物半导体材料的至少一层; （c）提供分离衬底和化合物半导体材料的至少一个中间层; 和（d）将化合物半导体材料排列成基本上不含通常建立预定部分的横向极限的化合物半导体材料的间隔。

公开(公告)号：US20030036224A1

公开(公告)日：2003-02-20

申请号：US09929021

申请日：2001-08-15

Applicant: MOTOROLA, INC.

Inventor： Jonathan F. Gorrell ,  Kenneth D. Cornett

IPC: H01L021/00 ,  H01L021/84 ,  H01L021/338 ,  H01L021/336

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L27/0605

Abstract: A method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantially planar face displaced from the plurality of lands by a predetermined distance.

Abstract translation: 一种用于制造包括多个共面平面的多个材料的整体式装置的方法包括以下步骤：（a）提供由第一材料构成并呈现第一焊盘的基板; （b）将衬底开沟以实现适当尺寸的接纳半导体结构的腔，所述半导体结构呈现出与第一焊盘大致共面的第二焊盘; （c）在所述基底上并在所述腔内沉积由第二材料构成的容纳层以建立工件; （d）在基板上沉积由第三材料构成的组合物层; （e）选择性地去除组合物层和容纳层的部分以建立半导体结构; （f）在工件上沉积由第四材料构成的盖层; 和（g）去除所述盖层以建立从所述多个焊盘移位预定距离的基本平坦的面。

公开(公告)号：US20030012925A1

公开(公告)日：2003-01-16

申请号：US09905110

申请日：2001-07-16

Applicant: MOTOROLA, INC.

Inventor： Jonathan F. Gorrell

IPC: H01L031/112 ,  B32B003/10 ,  H01L029/76 ,  H01L031/036

CPC classification number: H01L21/76898 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/30608 ,  H01L21/31111 ,  H01L21/8258 ,  H01L27/0605 ,  H01L2924/0002 ,  Y10T428/24322 ,  Y10T428/24331 ,  H01L2924/00

Abstract: Highly controlled, highly aligned monolithic integration of devices in a high quality monocrystalline material layer (26) with vias (211, 231) fabricated in an underlying monocrystalline substrate (22) in a single monolithic three dimensional architecture (20, 34). Excellent compliancy is achieved in a monolithic semiconductor structure (20, 34) by processes described herein while at the same time fabrication of via openings (211, 231) in the monocrystalline substrate (20, 34) can be made in a controlled, aligned manner to the back side (263) of a high quality monocrystalline film (26). Conductive connections (219, 239) can be made to devices (271, 273) in the high quality monocrystalline layer (26) from its backside (263).

Abstract translation: 高度对齐的高度对齐的单体集成器件在高质量的单晶材料层（26）中，其中通孔（211,231）在单个单片三维架构（20,34）中制造在下面的单晶衬底（22）中。 通过本文所述的工艺，在单片半导体结构（20,34）中实现了优异的兼容性，同时可以以受控对准的方式制造单晶衬底（20,34）中的通孔开口（211,231），同时 到高质量单晶膜（26）的背面（263）。 导电连接（219,239）可以从其背面（263）制成高质量单晶层（26）中的器件（271,273）。