公开(公告)号：US20190198630A1

公开(公告)日：2019-06-27

申请号：US15849971

申请日：2017-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Chien-Ying Lee ,  Chih-Hsiung Lee ,  Tzung-Ting Han

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L27/11521

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11521 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883

Abstract: Methods of managing gate coupling for semiconductor devices, e.g., non-volatile memory devices, are provided. The methods include: providing a conductive layer on a semiconductor substrate, the conductive layer including a lower conductive layer and an upper conductive layer, the lower conductive layer including a first material and the upper conductive layer including a second material having at least one property different from the first material, forming a protective pattern on the conductive layer, and etching through the conductive layer to obtain individual separated gates by controlling an etching process such that the first material has a higher etching rate than the second material during the etching process, each of the gates including an upper gate and a lower gate, the lower gate having a smaller width than the upper gate after the etching process.

公开(公告)号：US09899396B1

公开(公告)日：2018-02-20

申请号：US15366682

申请日：2016-12-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Hsiung Lee ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L27/088 ,  H01L27/11524 ,  H01L27/11548 ,  H01L21/762 ,  H01L29/788 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L27/11531 ,  H01L27/11548

Abstract: A method for fabricating a semiconductor device includes: forming a first trench and a wider second trench in a substrate and a material layer formed thereon, forming a flowable isolation material covering the material layer and filling in the first and second trenches, removing a portion of the flowable isolation material in the second trench so that the thickness of the remaining flowable isolation material on the sidewall of the second trench is 200 Å to 1000 Å, and forming a non-flowable isolation material on the flowable isolation material.

公开(公告)号：US20220123009A1

公开(公告)日：2022-04-21

申请号：US17075480

申请日：2020-10-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Chien-Ying Lee ,  Chih-Hsiung Lee ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Provided is a memory device including a substrate, a stack structure on the substrate, a contact, and a supporting pillar. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The contact is connected to one of the plurality of conductive layers of the stack structure. The supporting pillar penetrates the stack structure and is disposed around the contact. The supporting pillar includes a body portion and a plurality of extension portions. The body portion is arranged around a first side of the contact. The plurality of extension portions are located on two sides of the body portion. A length of each of the extension portions is greater than a width of the contact, and one of the extension portions is disposed around a second side of the contact.

公开(公告)号：US09847339B2

公开(公告)日：2017-12-19

申请号：US15096560

申请日：2016-04-12

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Min Hung ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L21/768 ,  H01L27/11521 ,  H01L23/528 ,  H01L29/788 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L27/11521 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L28/00 ,  H01L29/7883

Abstract: Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.

公开(公告)号：US11637125B2

公开(公告)日：2023-04-25

申请号：US17075480

申请日：2020-10-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Chien-Ying Lee ,  Chih-Hsiung Lee ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: Provided is a memory device including a substrate, a stack structure on the substrate, a contact, and a supporting pillar. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The contact is connected to one of the plurality of conductive layers of the stack structure. The supporting pillar penetrates the stack structure and is disposed around the contact. The supporting pillar includes a body portion and a plurality of extension portions. The body portion is arranged around a first side of the contact. The plurality of extension portions are located on two sides of the body portion. A length of each of the extension portions is greater than a width of the contact, and one of the extension portions is disposed around a second side of the contact.

公开(公告)号：US20170294442A1

公开(公告)日：2017-10-12

申请号：US15096560

申请日：2016-04-12

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Min Hung ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L28/00 ,  H01L29/7883

Abstract: Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.

公开(公告)号：US20160020143A1

公开(公告)日：2016-01-21

申请号：US14334363

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Chien-Ying Lee ,  Chih-Hsiung Lee ,  Tzung-Ting Han

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L29/66825 ,  H01L27/11521 ,  H01L29/7881

Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a first dielectric layer over buried oxide regions and the removal of such dielectric layer to prepare a substantially planar substrate for subsequent formation of word lines. The method may allow for the production of semiconductor memory devices of reduced size with reduced word line stringer residual material.

Abstract translation: 提供了用于制造这种半导体存储器件的改进的半导体存储器件和方法。 一种方法可以包括在掩埋氧化物区域上形成第一电介质层，以及去除这种电介质层以制备用于随后形成字线的基本平坦的衬底。 该方法可以允许使用减少的字线纵梁残余材料来生产尺寸减小的半导体存储器件。

公开(公告)号：US09070753B1

公开(公告)日：2015-06-30

申请号：US14327255

申请日：2014-07-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Hsiung Lee ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/7688 ,  H01L27/11573 ,  H01L29/66833

Abstract: Provided is a method for fabricating a memory device. A stack layer, including a storage layer, a first conductive layer and a first mask layer, is formed on the substrate in a first region and a second region. The stack layer is patterned to form a plurality of first patterned stack layers extending along a first direction and from the first region to the second region. Two sides of each first patterned stack layers have openings respectively. A filling layer is formed on the substrate, and filled in the openings. A second mask layer is formed on the second region, and does not cover the filling layer in the second region. Then, using the second mask layer and the filling layer as mask, the first patterned stack layers and part of the substrate are removed, and a plurality of trenches are formed in the substrate in the second region.

Abstract translation: 提供一种用于制造存储器件的方法。 在第一区域和第二区域中的衬底上形成包括存储层，第一导电层和第一掩模层的堆叠层。 图案化堆叠层以形成沿着第一方向从第一区域延伸到第二区域的多个第一图案化堆叠层。 每个第一图案化叠层的两侧分别具有开口。 填充层形成在基板上并填充在开口中。 第二掩模层形成在第二区域上，并且不覆盖第二区域中的填充层。 然后，使用第二掩模层和填充层作为掩模，去除第一图案化堆叠层和衬底的一部分，并且在第二区域中的衬底中形成多个沟槽。