公开(公告)号：US20160204697A1

公开(公告)日：2016-07-14

申请号：US14693565

申请日：2015-04-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Yi-Fan Chang ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: H02M3/10 ,  H03K17/30

CPC classification number: H03K17/007 ,  G11C8/00 ,  G11C8/10 ,  H03K2217/0036

Abstract: A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.

Abstract translation: 提供了解码开关和用于控制解码开关的方法。 解码开关包括提供第一电压的电源，耦合到电源的源电容和耦合到电源的目标电容。 电源将源电容充电到第一电压。 源电容连接到目标电容，源电容将目标电容充电到第二电压。 电源将目标电容从第二电压充电到第一电压。

公开(公告)号：US09881654B2

公开(公告)日：2018-01-30

申请号：US14877723

申请日：2015-10-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wu-Chin Peng ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun Hsiung Hung

IPC: G11C5/14

CPC classification number: G11C5/145

Abstract: An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.

公开(公告)号：US09876493B2

公开(公告)日：2018-01-23

申请号：US14693565

申请日：2015-04-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Yi-Fan Chang ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C8/00 ,  H03K17/00 ,  G11C8/10

CPC classification number: H03K17/007 ,  G11C8/00 ,  G11C8/10 ,  H03K2217/0036

Abstract: A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.

公开(公告)号：US09628061B2

公开(公告)日：2017-04-18

申请号：US14860761

申请日：2015-09-22

Applicant: Macronix International Co., Ltd.

Inventor： Kuan-Ming Lu ,  Chun-Hsiung Hung ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: H03K5/153 ,  H03K5/1534

CPC classification number: H03K5/1534

Abstract: A power drop detector circuit includes a detect element, for coupling to a first source voltage, for detecting a voltage level of the first source voltage, and a memory element coupled to the detect element and switchable between a first memory state and a second memory state based on the voltage level of the first source voltage.

公开(公告)号：US09536575B2

公开(公告)日：2017-01-03

申请号：US14877692

申请日：2015-10-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wu-Chin Peng ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun Hsiung Hung

IPC: G11C7/12 ,  G11C5/14

CPC classification number: G11C5/145 ,  G11C7/12 ,  G11C8/08

Abstract: An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.

Abstract translation: 集成电路包括用于接收可以具有可变电流的芯片外电源电压的电源输入引脚，由芯片外电源电压供电并且可以提供调节电流的片上电源，一组 一个或多个电路由芯片外电源电压和片上电源中的至少一个供电;配置存储器，存储一组或多个存储器设置，其指示所述一组或多个电路 更多的电路由片上电源供电，以及响应于至少一个存储器设置的控制电路，以控制所述一组或多个电路的所述电路是否由片上电源供电。

公开(公告)号：US20150036436A1

公开(公告)日：2015-02-05

申请号：US14518645

申请日：2014-10-20

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/16 ,  G11C16/344

Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

Abstract translation: 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

公开(公告)号：US09502121B2

公开(公告)日：2016-11-22

申请号：US14518645

申请日：2014-10-20

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C16/14 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/16 ,  G11C16/344

Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

Abstract translation: 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。