公开(公告)号：US20160027729A1

公开(公告)日：2016-01-28

申请号：US14341351

申请日：2014-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Lu Chen ,  Shih-Ping Hong ,  Ta Hung Yang

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.

Abstract translation: 半导体互连结构形成为具有倒T形的通孔，以增加互连结构和下面的导电（例如铜（Cu））材料层之间的界面的可靠性。 倒T形有效地增加了通孔的底部临界尺寸，从而通过在高温或应力迁移烘烤期间导入的导电层中的空隙引起的互连结构的降解和/或消除。

公开(公告)号：US09252153B1

公开(公告)日：2016-02-02

申请号：US14493021

申请日：2014-09-22

Applicant: Macronix International Co., Ltd.

Inventor： Cheng-Yi Lung ,  An-Chyi Wei ,  Ta Hung Yang

IPC: H01L29/66 ,  H01L29/76 ,  H01L27/088 ,  H01L27/115 ,  H01L29/51 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/792 ,  H01L23/528

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semi-damascene method is described for fabricating wordlines without stringers while maintaining critical cell dimensions when wordline pitch is less than 40 nm. A thin conducting layer protects a storage layer during manufacture, the thin conducting layer then making contact with filled-in conducting material.

Abstract translation: 描述了一种半镶嵌方法，用于在没有桁条的情况下制造字线，同时在字线间距小于40nm时保持临界单元尺寸。 薄的导电层在制造过程中保护存储层，然后薄导电层与填充的导电材料接触。

公开(公告)号：US09905509B2

公开(公告)日：2018-02-27

申请号：US14341351

申请日：2014-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Lu Chen ,  Shih-Ping Hong ,  Ta Hung Yang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.