公开(公告)号：US09406609B1

公开(公告)日：2016-08-02

申请号：US14747856

申请日：2015-06-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Yi Lung

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L27/11548 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a manufacturing method of an opening structure, a multi-layer structure including alternately stacked conductive layers and first dielectric layers is formed on a substrate. The conductive layers in a first region are lower than those in a second region. A second dielectric layer covering the multi-layer structure is formed. A patterned mask layer is formed on the second dielectric layer. A first filling layer covering the second dielectric layer exposed by the patterned mask layer is formed in the second region. First openings exposing the conductive layers in the first region are formed by using the first filling layer and the patterned mask layer as a mask. The first filling layer is removed. A second filling layer filling the first openings is formed. Second openings exposing the conductive layers in the second region are formed by using the second filling layer and the patterned mask layer as a mask.

Abstract translation: 在开口结构的制造方法中，在基板上形成包括交替层叠的导电层和第一电介质层的多层结构。 第一区域中的导电层低于第二区域中的导电层。 形成覆盖多层结构的第二电介质层。 图案化的掩模层形成在第二介电层上。 覆盖由图案化掩模层露出的第二电介质层的第一填充层形成在第二区域中。 通过使用第一填充层和图案化掩模层作为掩模来形成暴露第一区域中的导电层的第一开口。 第一填充层被去除。 形成填充第一开口的第二填充层。 通过使用第二填充层和图案化掩模层作为掩模来形成暴露第二区域中的导电层的第二开口。

公开(公告)号：US20160086968A1

公开(公告)日：2016-03-24

申请号：US14490137

申请日：2014-09-18

Applicant: MACRONIX International Co., Ltd.

Inventor： Zu-Sing Yang ,  Cheng-Yi Lung

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of stack structures, and a plurality of support layers. The stack structures are disposed on the substrate, and a trench is formed between adjacent two stack structures. Each of the stack structures includes a plurality of conductor layers and a plurality of dielectric layers. The dielectric layers and the conductor layers are disposed alternately. The support layers are disposed in the stack structures respectively.

Abstract translation: 提供半导体器件。 半导体器件包括衬底，多个堆叠结构和多个支撑层。 堆叠结构设置在衬底上，并且在相邻的两个堆叠结构之间形成沟槽。 每个堆叠结构包括多个导体层和多个电介质层。 电介质层和导体层交替设置。 支撑层分别设置在堆叠结构中。

公开(公告)号：US09252153B1

公开(公告)日：2016-02-02

申请号：US14493021

申请日：2014-09-22

Applicant: Macronix International Co., Ltd.

Inventor： Cheng-Yi Lung ,  An-Chyi Wei ,  Ta Hung Yang

IPC: H01L29/66 ,  H01L29/76 ,  H01L27/088 ,  H01L27/115 ,  H01L29/51 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/792 ,  H01L23/528

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semi-damascene method is described for fabricating wordlines without stringers while maintaining critical cell dimensions when wordline pitch is less than 40 nm. A thin conducting layer protects a storage layer during manufacture, the thin conducting layer then making contact with filled-in conducting material.

Abstract translation: 描述了一种半镶嵌方法，用于在没有桁条的情况下制造字线，同时在字线间距小于40nm时保持临界单元尺寸。 薄的导电层在制造过程中保护存储层，然后薄导电层与填充的导电材料接触。