公开(公告)号：US09210009B2

公开(公告)日：2015-12-08

申请号：US13618607

申请日：2012-09-14

申请人： Majid Pashay-Kojouri ,  Richard Maiden

发明人： Majid Pashay-Kojouri ,  Richard Maiden

IPC分类号： H04B15/00 ,  H04L25/03 ,  H04L27/26 ,  H03F3/193 ,  H03F3/45 ,  H04L27/36 ,  H03F1/32

CPC分类号： H04L25/49 ,  H03F1/3241 ,  H03F3/193 ,  H03F3/45179 ,  H03F2200/405 ,  H03F2203/45318 ,  H03F2203/45332 ,  H03F2203/45394 ,  H04B15/00 ,  H04L25/03343 ,  H04L25/03834 ,  H04L27/2614 ,  H04L27/367 ,  H04L2025/03414 ,  H04L2025/03503

摘要： A digital predistorter for improving the performance of a narrow passband filter near the output is disclosed. The digital predistorter provides amplitude correction to the signal based on the characteristics of the passband filter. A filter group delay predistorter may also be employed to correct group delay variation introduced by the narrow passband filter.

摘要翻译： 公开了一种用于改善输出附近的窄通带滤波器的性能的数字预失真器。 数字预失真器基于通带滤波器的特性向信号提供幅度校正。 还可以采用滤波器组延迟预失真器来校正由窄通带滤波器引入的群延迟变化。

公开(公告)号：US20240345161A1

公开(公告)日：2024-10-17

申请号：US18756925

申请日：2024-06-27

申请人： Richard Maiden ,  Ankur Vora ,  Hans Brandberg ,  Kishan Shenoi

发明人： Richard Maiden ,  Ankur Vora ,  Hans Brandberg ,  Kishan Shenoi

IPC分类号： G01R31/317 ,  H03L7/08

CPC分类号： G01R31/31727 ,  H03L7/08

摘要： Systems and methods for controlling clock drift of an integrated circuit device are provided. Such a system may include a local oscillator to provide a reference clock signal, a phase-locked loop to provide a system clock signal based on the reference clock signal and a drift control signal, and processing circuitry to generate the drift control signal. In a synchronization mode, the processing circuitry may generate the drift control signal based on an input time reference signal. In a holdover mode, the processing circuitry may generate the drift control signal based on a trained machine learning model.

公开(公告)号：US20200026747A1

公开(公告)日：2020-01-23

申请号：US16586669

申请日：2019-09-27

申请人： Hong Cheng ,  Xu Zhang ,  Richard Maiden ,  Long Jiang

发明人： Hong Cheng ,  Xu Zhang ,  Richard Maiden ,  Long Jiang

IPC分类号： G06F17/16

摘要： A system is provided, a circuitry comprising a plurality of processing elements (PEs) and configured to receive as input entries of a Hermitian positive-definite matrix A. The circuitry is also configured to Cholesky decompose the matrix A by deriving an intermediate numerator for at least one of the entries. The circuitry is additionally configured to calculate a square root for the intermediate numerator and to derive as an output an entry of a lower triangular matrix L based on the square root, wherein A=LL*, and wherein L* is a conjugate transpose of the lower triangular matrix L.