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1.发明申请公开(公告)号：US20180144797A1
公开(公告)日：2018-05-24
申请号：US15356277
申请日：2016-11-18
IPC分类号： G11C13/00
CPC分类号： G11C13/0026 , G11C7/04 , G11C13/0002 , G11C13/0011 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.
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公开(公告)号：US20080083918A1
公开(公告)日：2008-04-10
申请号：US11632594
申请日：2005-07-08
IPC分类号： H01L45/00
CPC分类号： G11C13/0011 , G11C13/0069 , G11C2013/009 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： It is intended to provide a storage element having an arrangement which becomes able to be manufactured easily with high density.A storage element includes resistance changing elements 10 having recording layers 2, 3 provided between two electrodes 1, 4 and in which resistance values of the recording layers 2, 3 are reversibly changed with application of electric potential with different polarities to these two electrodes 1, 4, at least part of the layers 2, 3 constructing the recording layers of the resistance changing elements 10 being formed commonly by the same layer in a plurality of adjacent memory cells.
摘要翻译： 旨在提供具有能够以高密度容易地制造的布置的存储元件。 存储元件包括电阻变化元件10，其具有设置在两个电极1,4之间的记录层2,3，并且其中记录层2,3的电阻值可通过向这两个电极1施加不同极性的电位而可逆地改变， 如图4所示，构成电阻变化元件10的记录层的层2,3的至少一部分由多个相邻存储单元中的相同层共同形成。
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公开(公告)号：US07242606B2
公开(公告)日：2007-07-10
申请号：US11225593
申请日：2005-09-13
申请人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
发明人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C13/02 , G11C13/0069 , G11C2213/79
摘要： A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
摘要翻译： 一种存储装置，具有各自具有存储元件的存储器件，该存储元件具有不低于第一阈值信号的电信号的施加使得存储元件从高电阻值状态向低电阻值状态移动的特征， 施加不低于第一阈值信号极性的第二阈值信号的电信号允许存储元件从低电阻值状态移位到高电阻值状态，并且连接的电路元件 将串联的存储元件作为负载; 其中所述存储器件被布置在矩阵中，并且每个所述存储器件的一个端子连接到公共线; 并且其中电源电位和接地电位之间的中间电位被施加到公共线。
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公开(公告)号：US07560724B2
公开(公告)日：2009-07-14
申请号：US11632594
申请日：2005-07-08
CPC分类号： G11C13/0011 , G11C13/0069 , G11C2013/009 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： It is intended to provide a storage element having an arrangement which becomes able to be manufactured easily with high density. A storage element includes resistance changing elements 10 having recording layers 2, 3 provided between two electrodes 1, 4 and in which resistance values of the recording layers 2, 3 are reversibly changed with application of electric potential with different polarities to these two electrodes 1, 4, at least part of the layers 2, 3 constructing the recording layers of the resistance changing elements 10 being formed commonly by the same layer in a plurality of adjacent memory cells.
摘要翻译： 旨在提供具有能够以高密度容易地制造的布置的存储元件。 存储元件包括电阻变化元件10，其具有设置在两个电极1,4之间的记录层2,3，并且其中记录层2,3的电阻值可通过向这两个电极1施加不同极性的电位而可逆地改变， 如图4所示，构成电阻变化元件10的记录层的层2,3的至少一部分由多个相邻存储单元中的相同层共同形成。
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公开(公告)号：US20060067114A1
公开(公告)日：2006-03-30
申请号：US11225593
申请日：2005-09-13
申请人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
发明人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C13/02 , G11C13/0069 , G11C2213/79
摘要： A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
摘要翻译： 一种存储装置，具有各自具有存储元件的存储器件，该存储元件具有不低于第一阈值信号的电信号的施加使得存储元件从高电阻值状态向低电阻值状态移动的特征， 施加不低于第一阈值信号极性的第二阈值信号的电信号允许存储元件从低电阻值状态移位到高电阻值状态，并且连接的电路元件 将串联的存储元件作为负载; 其中所述存储器件被布置在矩阵中，并且每个所述存储器件的一个端子连接到公共线; 并且其中电源电位和接地电位之间的中间电位被施加到公共线。
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6.发明申请Semiconductor memory device, sense amplifier circuit and memory cell reading method 有权半导体存储器件，读出放大器电路和存储单元读取方法公开(公告)号：US20080165592A1
公开(公告)日：2008-07-10
申请号：US11984813
申请日：2007-11-21
申请人： Makoto Kitagawa , Wataru Otsuka
发明人： Makoto Kitagawa , Wataru Otsuka
IPC分类号： G11C7/00
CPC分类号： G11C11/16
摘要： A semiconductor memory device includes: a memory cell; a sense line; and a sense amplifier circuit connected to the memory cell via the sense line. The sense amplifier circuit includes a differential sense amplifier, a pull-up section, a read gate transistor, and a threshold correction section.
摘要翻译： 半导体存储器件包括：存储单元; 感觉线; 以及通过感测线连接到存储单元的读出放大器电路。 读出放大器电路包括差分读出放大器，上拉部分，读取栅极晶体管和阈值校正部分。
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公开(公告)号：US08144499B2
公开(公告)日：2012-03-27
申请号：US12654484
申请日：2009-12-22
CPC分类号： G11C13/0009 , G11C11/56 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2213/11 , G11C2213/33 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： A variable resistance memory device includes: a first common line; a second common line; plural memory cells each formed by serially connecting a memory element, resistance of which changes according to applied voltage, and an access transistor between the second common line and the first common line; a common line pass transistor connected between the first common line and a supply node for predetermined voltage; and a driving circuit that controls voltage of the second common line, the predetermined voltage, and voltage of a control node of the common line pass transistor and drives the memory cells.
摘要翻译： 可变电阻存储器件包括：第一公共线; 第二条共同线 每个存储单元通过串联连接存储元件，其电阻根据施加的电压而变化，以及第二公共线与第一公共线之间的存取晶体管， 连接在第一公共线和供电节点之间的公共线路传输晶体管用于预定电压; 以及驱动电路，其控制公共线路通过晶体管的控制节点的第二公共线的电压，预定电压和电压，并驱动存储单元。
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8.发明授权Semiconductor memory device, sense amplifier circuit and memory cell reading method using a threshold correction circuitry 有权半导体存储器件，读出放大器电路和使用阈值校正电路的存储单元读取方法公开(公告)号：US07916556B2
公开(公告)日：2011-03-29
申请号：US11984813
申请日：2007-11-21
申请人： Makoto Kitagawa , Wataru Otsuka
发明人： Makoto Kitagawa , Wataru Otsuka
IPC分类号： G11C7/06
CPC分类号： G11C11/16
摘要： A semiconductor memory device includes: a memory cell; a sense line; and a sense amplifier circuit connected to the memory cell via the sense line. The sense amplifier circuit includes a differential sense amplifier, a pull-up section, a read gate transistor, and a threshold correction section.
摘要翻译： 半导体存储器件包括：存储单元; 感觉线; 以及通过感测线连接到存储器单元的读出放大器电路。 读出放大器电路包括差分读出放大器，上拉部分，读取栅极晶体管和阈值校正部分。
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公开(公告)号：US20100182820A1
公开(公告)日：2010-07-22
申请号：US12654484
申请日：2009-12-22
CPC分类号： G11C13/0009 , G11C11/56 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2213/11 , G11C2213/33 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： A variable resistance memory device includes: a first common line; a second common line; plural memory cells each formed by serially connecting a memory element, resistance of which changes according to applied voltage, and an access transistor between the second common line and the first common line; a common line pass transistor connected between the first common line and a supply node for predetermined voltage; and a driving circuit that controls voltage of the second common line, the predetermined voltage, and voltage of a control node of the common line pass transistor and drives the memory cells.
摘要翻译： 可变电阻存储器件包括：第一公共线; 第二条共同线 每个存储单元通过串联连接存储元件，其电阻根据施加的电压而变化，以及第二公共线与第一公共线之间的存取晶体管， 连接在第一公共线和供电节点之间的公共线路传输晶体管用于预定电压; 以及驱动电路，其控制公共线路通过晶体管的控制节点的第二公共线的电压，预定电压和电压，并驱动存储单元。
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公开(公告)号：US20120182785A1
公开(公告)日：2012-07-19
申请号：US13337969
申请日：2011-12-27
申请人： Wataru Otsuka
发明人： Wataru Otsuka
IPC分类号： G11C11/21
CPC分类号： B65D71/14 , B65D71/125 , B65D2571/00907 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2213/15 , G11C2213/56 , G11C2213/74 , G11C2216/24
摘要： A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.
摘要翻译： 存储单元包括各自具有存储元件和晶体管，字线和第一和第二位线以及驱动部分的存储单元。 在对位于一个字线上的第一存储元件执行设定操作并对位于一个字线上的第二存储元件执行复位操作时，驱动部分将给定的字线电位施加到一个字线， 在与第一存储元件相对应的第一和第二位线之外的低电位侧的位线的电位高于对应于下一个电位侧的位线的电位值 第二存储元件以给定电位差的量。
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