公开(公告)号：US09029869B2

公开(公告)日：2015-05-12

申请号：US13034264

申请日：2011-02-24

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/15 ,  H01L29/739 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7395 ,  H01L29/1033 ,  H01L29/66333

摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅极绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。

公开(公告)号：US08012837B2

公开(公告)日：2011-09-06

申请号：US12716403

申请日：2010-03-03

申请人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

发明人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/265

CPC分类号： H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/0495 ,  H01L21/30604 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.

摘要翻译： 提供了即使当使用包括缺陷的碳化硅半导体时也能够实现大规模半导体器件的高产率的半导体器件的制造方法。 制造半导体器件的方法包括：在碳化硅半导体衬底上外延生长碳化硅半导体层的步骤; 抛光所述碳化硅半导体层的表面的步骤; 在抛光步骤之后将杂质离子注入到碳化硅半导体层中的步骤; 进行热处理以活化杂质的步骤; 在进行热处理的步骤之后，在碳化硅半导体层的表面上形成第一热氧化膜的工序; 化学去除第一热氧化膜的步骤; 以及在所述碳化硅半导体膜上形成电极层的步骤。

公开(公告)号：US20110175106A1

公开(公告)日：2011-07-21

申请号：US12716386

申请日：2010-03-03

申请人： Makoto MIZUKAMI ,  Takashi Shinohe ,  Johji Nishio

发明人： Makoto MIZUKAMI ,  Takashi Shinohe ,  Johji Nishio

IPC分类号： H01L29/24

CPC分类号： H01L29/1608 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/45 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor rectifier includes: a wide bandgap semiconductor substrate of a first conductivity type; a wide bandgap semiconductor layer of the first conductivity type which is formed on an upper surface of the wide bandgap semiconductor substrate and has an impurity concentration of 1E+14 atoms/cm3 or more and 5E+16 atoms/cm3 or less and a thickness of 20 μm or more; a first wide bandgap semiconductor region of the first conductivity type formed on a surface of the wide bandgap semiconductor layer; a second wide bandgap semiconductor region of a second conductivity type formed to be sandwiched by the first wide bandgap semiconductor regions; a first electrode formed on the first and second wide bandgap semiconductor regions; and a second electrode formed on a lower surface of the wide bandgap semiconductor substrate, wherein a width of the second wide bandgap semiconductor region is 15 μm or more.

摘要翻译： 半导体整流器包括：第一导电类型的宽带隙半导体衬底; 第一导电类型的宽带隙半导体层形成在宽带隙半导体衬底的上表面上，杂质浓度为1E + 14原子/厘米3以上且5E + 16原子/ cm 3以下，厚度为 20μm以上; 形成在宽带隙半导体层的表面上的第一导电类型的第一宽带隙半导体区域; 形成为被第一宽带隙半导体区域夹持的第二导电类型的第二宽带隙半导体区域; 形成在所述第一宽带隙半导体区域和所述第二宽带隙半导体区域上的第一电极; 以及形成在宽带隙半导体衬底的下表面上的第二电极，其中第二宽带隙半导体区域的宽度为15μm以上。

公开(公告)号：US08227811B2

公开(公告)日：2012-07-24

申请号：US13036940

申请日：2011-02-28

申请人： Makoto Mizukami ,  Johji Nishio

发明人： Makoto Mizukami ,  Johji Nishio

IPC分类号： H01L31/0312

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/1608

摘要： A wide bandgap semiconductor rectifying device of an embodiment includes a first-conductive-type wide bandgap semiconductor substrate and a first-conductive-type semiconductor layer that has an impurity concentration lower than that of the substrate. The device also includes a first-conductive-type first semiconductor region, and a second-conductive-type second semiconductor region that is formed between the first regions. The device also includes second-conductive-type third semiconductor regions in which at least part of the third regions are connected to the second wide bandgap semiconductor region, the third regions being formed between the first regions, the third regions having a width narrower than that of the second region. The device also includes a first electrode and a second electrode. In the device, a direction in which a longitudinal direction of the third regions are projected onto a (0001) plane of the layer has an angle of 90±30 degrees with respect to a direction of the layer. A gap between the third regions is not lower than 2d×tan 18°, where d is a thickness of the layer.

摘要翻译： 实施例的宽带隙半导体整流装置包括第一导电型宽带隙半导体衬底和杂质浓度低于衬底的杂质浓度的第一导电型半导体层。 该器件还包括形成在第一区域之间的第一导电型第一半导体区域和第二导电型第二半导体区域。 该器件还包括第二导电类型的第三半导体区域，其中至少一部分第三区域连接到第二宽带隙半导体区域，第三区域形成在第一区域之间，第三区域宽度窄于第一区域。 的第二个地区。 该装置还包括第一电极和第二电极。 在该装置中，第三区域的纵向方向投影到层的（0001）平面上的方向相对于层的<11-20>方向具有90±30度的角度。 第三区域之间的间隙不低于2d×tan 18°，其中d是层的厚度。

公开(公告)号：US20120056196A1

公开(公告)日：2012-03-08

申请号：US13034297

申请日：2011-02-24

申请人： Chiharu Ota ,  Takashi Shinohe ,  Makoto Mizukami ,  Johji Nishio

发明人： Chiharu Ota ,  Takashi Shinohe ,  Makoto Mizukami ,  Johji Nishio

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/26513 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer. The semiconductor device also includes a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode while being in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substrate.

摘要翻译： 根据实施例的半导体器件包括第一导电型半导体衬底; 形成在半导体衬底上的第一导电型第一半导体层，其杂质浓度低于半导体衬底的杂质浓度; 外延形成在第一半导体层上的第二导电型第二半导体层; 以及外延形成在所述第二半导体层上，并且具有比所述第二半导体层的杂质浓度高的杂质浓度的第二导电型第三半导体层。 半导体器件还包括形成在第三半导体层中的凹部，并且至少侧面和底面的角部位于第二半导体层中。 半导体器件还包括与第三半导体层接触的第一电极; 第二电极，其与所述第一电极连接，同时在所述凹部的底表面处与所述第二半导体层接触; 以及与半导体衬底的下表面接触的第三电极。

公开(公告)号：US20120056195A1

公开(公告)日：2012-03-08

申请号：US13034264

申请日：2011-02-24

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/161

CPC分类号： H01L29/7395 ,  H01L29/1033 ,  H01L29/66333

摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。

公开(公告)号：US20110059597A1

公开(公告)日：2011-03-10

申请号：US12716403

申请日：2010-03-03

申请人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

发明人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L21/20

CPC分类号： H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/0495 ,  H01L21/30604 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.

摘要翻译： 提供了即使当使用包括缺陷的碳化硅半导体时也能够实现大规模半导体器件的高产率的半导体器件的制造方法。 制造半导体器件的方法包括：在碳化硅半导体衬底上外延生长碳化硅半导体层的步骤; 抛光所述碳化硅半导体层的表面的步骤; 在抛光步骤之后将杂质离子注入到碳化硅半导体层中的步骤; 进行热处理以活化杂质的步骤; 在进行热处理的步骤之后，在碳化硅半导体层的表面上形成第一热氧化膜的工序; 化学去除第一热氧化膜的步骤; 以及在所述碳化硅半导体膜上形成电极层的步骤。

公开(公告)号：US08823148B2

公开(公告)日：2014-09-02

申请号：US13034297

申请日：2011-02-24

申请人： Chiharu Ota ,  Takashi Shinohe ,  Makoto Mizukami ,  Johji Nishio

发明人： Chiharu Ota ,  Takashi Shinohe ,  Makoto Mizukami ,  Johji Nishio

IPC分类号： H01L29/868 ,  H01L29/861 ,  H01L29/66 ,  H01L29/872 ,  H01L29/16

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/26513 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device includes a first-conductivity-type semiconductor substrate; a first-conductivity-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductivity-type second semiconductor layer epitaxially formed on the first semiconductor layer; a second-conductivity-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer; a recess formed in the third semiconductor layer, at least a corner portion of a side face and a bottom surface of the recess being located in the second semiconductor layer; a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode and in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substrate.

摘要翻译： 半导体器件包括第一导电型半导体衬底; 形成在半导体衬底上的第一导电型第一半导体层，其杂质浓度低于半导体衬底的杂质浓度; 外延形成在第一半导体层上的第二导电型第二半导体层; 外延形成在第二半导体层上，并且杂质浓度高于第二半导体层的杂质浓度的第二导电型第三半导体层; 形成在所述第三半导体层中的凹部，所述凹部的至少侧面的角部和所述凹部的底面位于所述第二半导体层中; 与第三半导体层接触的第一电极; 连接到所述第一电极并在所述凹部的底表面处与所述第二半导体层接触的第二电极; 以及与半导体衬底的下表面接触的第三电极。

公开(公告)号：US08686437B2

公开(公告)日：2014-04-01

申请号：US13601408

申请日：2012-08-31

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/15

CPC分类号： H01L21/0465 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7827

摘要： According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration.

摘要翻译： 根据一个实施例，半导体器件包括第一，第二，第三，第四和第五半导体区域，绝缘膜，控制电极以及第一和第二电极。 第一，第二，第三，第四和第五半导体区域包括碳化硅。 第一半导体区域具有第一杂质浓度，并且具有第一部分。 第二半导体区域设置在第一半导体区域上。 第三半导体区域设置在第二半导体区域上。 第四半导体区域设置在第一部分和第二半导体区域之间。 第四半导体区域设置在第一部分和第三半导体区域之间。 第五半导体区域包括设置在第一部分和第二半导体区域之间的第一区域，并且具有高于第一杂质浓度的第二杂质浓度。

公开(公告)号：US20130234158A1

公开(公告)日：2013-09-12

申请号：US13601408

申请日：2012-08-31

申请人： Hiroshi KONO ,  Takashi Shinohe ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi KONO ,  Takashi Shinohe ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/16 ,  H01L29/66

CPC分类号： H01L21/0465 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7827

摘要： According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration.

摘要翻译： 根据一个实施例，半导体器件包括第一，第二，第三，第四和第五半导体区域，绝缘膜，控制电极以及第一和第二电极。 第一，第二，第三，第四和第五半导体区域包括碳化硅。 第一半导体区域具有第一杂质浓度，并具有第一部分。 第二半导体区域设置在第一半导体区域上。 第三半导体区域设置在第二半导体区域上。 第四半导体区域设置在第一部分和第二半导体区域之间。 第四半导体区域设置在第一部分和第三半导体区域之间。 第五半导体区域包括设置在第一部分和第二半导体区域之间的第一区域，并且具有高于第一杂质浓度的第二杂质浓度。