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    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08017975B2

    公开(公告)日：2011-09-13

    申请号：US12400376

    申请日：2009-03-09

    申请人： Keiichi Murayama ,  Akiyoshi Tamura ,  Hirotaka Miyamoto ,  Kenichi Miyajima

    发明人： Keiichi Murayama ,  Akiyoshi Tamura ,  Hirotaka Miyamoto ,  Kenichi Miyajima

    IPC分类号： H01L29/66

    CPC分类号： H01L27/0623 ,  H01L21/8248 ,  H01L27/0605 ,  H01L29/7371 ,  H01L29/802

    摘要： A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.

    摘要翻译： 半导体器件和制造方法满足HBT和HFET两者的折衷特性优点。 该半导体器件是HBT和HFET集成电路。 HBT包括依次堆叠的子集电极层，GaAs集电极层，GaAs基极层和InGaP发射极层。 子集电极层包括GaAs外部副集电极区域和设置在GaAs外部子集电极区域上的GaAs内部子集电极区域。 在GaAs外部副集电极区域上分别形成台状集电体部和集电极。 HFET包括GaAs覆盖层，源电极和漏电极。 GaAs覆盖层包括GaAs外部副集电极区域的一部分。 源电极和漏极形成在GaAs盖层上。

    Hetero-junction bipolar transistor and manufacturing method thereof
    3.
    发明授权
    Hetero-junction bipolar transistor and manufacturing method thereof 有权
    异质结双极晶体管及其制造方法

    公开(公告)号：US07176099B2

    公开(公告)日：2007-02-13

    申请号：US11100511

    申请日：2005-04-07

    申请人： Keiichi Murayama ,  Akiyoshi Tamura ,  Masanobu Nogome

    发明人： Keiichi Murayama ,  Akiyoshi Tamura ,  Masanobu Nogome

    IPC分类号： H01L21/8222

    CPC分类号： H01L29/0821 ,  H01L29/7371

    摘要： A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

    摘要翻译： 满足避免电位击穿所需的高电阻的异质结双极晶体管包括：由GaAs制成的n型子集电极层110; 形成在副集电极层110上的由具有比亚集电体110的雪崩系数小的半导体材料制成的n型第一集电体121; 第二集电体层132由n型或i型GaAs制成，掺杂浓度低于副集电极层110的掺杂浓度，并形成在第一集电极层121上; 由GaAs制成并形成在第二集电层132上的p型基极层133; 以及由具有比基极层133的带隙大的带隙的半导体材料制成并且形成在基极层133上的发射极层134。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07091528B2

    公开(公告)日：2006-08-15

    申请号：US10902120

    申请日：2004-07-30

    申请人： Masanobu Nogome ,  Akiyoshi Tamura ,  Keiichi Murayama

    发明人： Masanobu Nogome ,  Akiyoshi Tamura ,  Keiichi Murayama

    IPC分类号： H01L31/328

    CPC分类号： H01L29/7371 ,  H01L29/0821

    摘要： A semiconductor device is provided having an improved breakdown voltage on high power output, the semiconductor device comprising a n-type GaAs subcollector layer, a n-type GaAs intermediate collector layer formed between a collector layer and the subcollector layer, the n-type GaAs collector layer, a p-type GaAs base layer, a n-type InGaP second emitter layer, a n-type GaAs first emitter layer, and a n-type InGaAs emitter contact layer, and a concentration of impurities in the intermediate collector layer is higher than a concentration of impurities in the collector layer and is lower than a concentration of impurities in the subcollector layer.

    摘要翻译： 提供了一种在高功率输出上具有改进的击穿电压的半导体器件，该半导体器件包括n型GaAs子集电极层，形成在集电极层和子集电极层之间的n型GaAs中间集电极层，n型GaAs 集电极层，p型GaAs基极层，n型InGaP第二发射极层，n型GaAs第一发射极层和n型InGaAs发射极接触层，中间集电极层中的杂质浓度为 高于集电体层中的杂质浓度，并且低于子集电极层中的杂质浓度。

    Pseudomorphic high electron mobility transistor with Schottky electrode including lanthanum and boron, and manufacturing method thereof
    5.
    发明授权
    Pseudomorphic high electron mobility transistor with Schottky electrode including lanthanum and boron, and manufacturing method thereof 失效
    包含镧和硼的肖特基电极的假晶高电子迁移率晶体管及其制造方法

    公开(公告)号：US06967360B2

    公开(公告)日：2005-11-22

    申请号：US10617793

    申请日：2003-07-14

    申请人： Yoshiharu Anda ,  Akiyoshi Tamura

    发明人： Yoshiharu Anda ,  Akiyoshi Tamura

    IPC分类号： H01L21/28 ,  H01L21/335 ,  H01L21/338 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01L31/0328

    CPC分类号： H01L29/66462 ,  H01L29/475 ,  H01L29/7784

    摘要： A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.

    摘要翻译： 一种半导体器件及其制造方法。 半导体器件具有半绝缘GaAs衬底310，形成在半绝缘GaAs衬底310上的GaAs缓冲层321，AlGaAs缓冲层322，沟道层323，间隔层324，载流子供应层325， 间隔层326，由未掺杂的In 0.48 Ga 0.52 P材料构成的肖特基层327和n + 栅电极330形成在肖特基层327上，由LaB 6构成，与肖特基层327具有肖特基接触，并且欧姆电极340形成在第n + +型GaAs覆盖层328。

    Semiconductor device having an MIS structure
    6.
    发明授权
    Semiconductor device having an MIS structure 失效
    具有MIS结构的半导体器件

    公开(公告)号：US5616947A

    公开(公告)日：1997-04-01

    申请号：US651322

    申请日：1996-05-31

    申请人： Akiyoshi Tamura

    发明人： Akiyoshi Tamura

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78

    CPC分类号： H01L29/517 ,  H01L21/28264 ,  H01L29/66522

    摘要： A semiconductor device including a GaAs semiconductor substrate, an insulating layer which is made of material selected from the group MgS, MgSSe and CaZnS and is formed on the GaAs substrate, and a conductive electrode formed on the insulating layer.

    摘要翻译： 包括GaAs半导体衬底的半导体器件，由GaAs衬底上形成的由MgS，MgSSe和CaZnS组成的材料制成的绝缘层，以及形成在绝缘层上的导电电极。

    Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof
    7.
    发明授权
    Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof 有权
    具有异质结双极晶体管的半导体器件及其制造方法

    公开(公告)号：US07989845B2

    公开(公告)日：2011-08-02

    申请号：US12126395

    申请日：2008-05-23

    申请人： Keiichi Murayama ,  Akiyoshi Tamura ,  Hirotaka Miyamoto ,  Kenichi Miyajima

    发明人： Keiichi Murayama ,  Akiyoshi Tamura ,  Hirotaka Miyamoto ,  Kenichi Miyajima

    IPC分类号： H01L31/0328

    CPC分类号： H01L27/0605 ,  H01L21/8249 ,  H01L21/8252 ,  H01L27/0623

    摘要： The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.

    摘要翻译： 本发明的目的是提供一种能够防止集电极击穿电压降低并且集电极电阻降低的半导体器件及其制造方法。 根据本发明的半导体器件包括：形成在半导体衬底的第一区域上的HBT; 以及形成在所述半导体衬底的第二区域上的HFET，其中所述HBT包括：具有第一导电性的发射极层; 具有比发射极层的带隙小的带隙的第二导电性的基底层; 第一电导率的集电极层或非掺杂集电极层; 以及在第一区域上依次形成的第一导电性的副集电极层，并且HFET包括包含发射极层的一部分的电子供体层和形成在电子供体层下面的沟道层。

    Semiconductor device and method for manufacturing the same
    8.
    发明申请
    Semiconductor device and method for manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20060237753A1

    公开(公告)日：2006-10-26

    申请号：US11388545

    申请日：2006-03-24

    申请人： Yoshiharu Anda ,  Akiyoshi Tamura ,  Mitsuru Nishitsuji

    发明人： Yoshiharu Anda ,  Akiyoshi Tamura ,  Mitsuru Nishitsuji

    IPC分类号： H01L31/112

    CPC分类号： H01L29/7784 ,  H01L21/28575 ,  H01L21/28587 ,  H01L29/66462

    摘要： A field effect transistor according to the present invention includes a channel layer formed above a semi-insulating substrate, a Schottky layer formed above the channel layer, a gate electrode formed on the Schottky layer, Ohmic contact layers that are located above the Schottky layer with the gate electrode interposed therebetween and formed of InGaAs, and a source electrode and a drain electrode that are formed on the Ohmic contact layers. The source electrode, the drain electrode and the gate electrode have a layered structure in which their corresponding layers are formed of the same material, a lowermost layer is a WSi layer and a layer containing Al is provided above the lowermost layer. A field effect transistor that has an electrode resistance equivalent to a conventional level and can reduce a cost of manufacturing a field effect transistor and a method for manufacturing the same are provided.

    摘要翻译： 根据本发明的场效应晶体管包括形成在半绝缘衬底上的沟道层，形成在沟道层上方的肖特基层，形成在肖特基层上的栅电极，位于肖特基层上方的欧姆接触层， 介于其间并由InGaAs形成的栅电极以及形成在欧姆接触层上的源电极和漏电极。 源电极，漏电极和栅电极具有层叠结构，其相应的层由相同的材料形成，最下层是WSi层，并且在最下层上设置含有Al的层。 提供具有等同于常规水平的电极电阻并且可以降低制造场效应晶体管的成本的场效应晶体管及其制造方法。

    Semiconductor device and manufacturing method thereof
    9.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US06982141B2

    公开(公告)日：2006-01-03

    申请号：US10937366

    申请日：2004-09-10

    申请人： Masanobu Nogome ,  Akiyoshi Tamura ,  Keiichi Murayama ,  Kazutsune Miyanaga ,  Yoshitaka Kuroishi

    发明人： Masanobu Nogome ,  Akiyoshi Tamura ,  Keiichi Murayama ,  Kazutsune Miyanaga ,  Yoshitaka Kuroishi

    IPC分类号： G03F7/00

    CPC分类号： H01L21/76898 ,  H01L21/8252 ,  H01L23/481 ,  H01L27/0605 ,  H01L2924/0002 ,  Y10S430/136 ,  H01L2924/00

    摘要： A GaAs substrate 200 is rotated, a photosensitive silicone resist 260 is applied on a surface of the GaAs substrate 200 on which an aperture of a hole 310 to be a via hole, and an inside of the hole 310 to be the via hole is filled in with the photosensitive silicone resist 260. Next, the GaAs substrate 200 is further rotated, changing the number of revolutions (rpm), and the photosensitive silicone resist 260 on the GaAs substrate is flattened. Next, a reverse side of the GaAs substrate is grinded, the hole 310 to be the via hole penetrates the GaAs substrate 200 from the surface to the reverse side and the via hole 220 is formed. Next, a reverse side electrode 240 is formed on the reverse side of the GaAs substrate 200. Next, the GaAs sustrate 200 is divided chip by chip and chips are laid on a substrate for assembly 270 via an adhesive metal 280.

    摘要翻译： 在GaAs衬底200旋转的同时，在GaAs衬底200的表面上施加感光性硅氧烷抗蚀剂260，在该衬底200的表面上填充孔310作为通孔的孔，填充孔310的内部 与感光性硅氧烷抗蚀剂260接触。接着，进一步旋转GaAs衬底200，改变转速（rpm），使GaAs衬底上的感光性硅氧烷抗蚀剂260变平。 接下来，研磨GaAs衬底的反面，作为通路孔的孔310从表面向反面侧穿过GaAs衬底200，形成通路孔220。 接下来，在GaAs衬底200的相反侧上形成反向侧电极240.接下来，将GaAs衬垫200逐个分割，并且通过粘合金属280将芯片放置在用于组件270的衬底上。