公开(公告)号：US20060237753A1

公开(公告)日：2006-10-26

申请号：US11388545

申请日：2006-03-24

申请人： Yoshiharu Anda ,  Akiyoshi Tamura ,  Mitsuru Nishitsuji

发明人： Yoshiharu Anda ,  Akiyoshi Tamura ,  Mitsuru Nishitsuji

IPC分类号： H01L31/112

CPC分类号： H01L29/7784 ,  H01L21/28575 ,  H01L21/28587 ,  H01L29/66462

摘要： A field effect transistor according to the present invention includes a channel layer formed above a semi-insulating substrate, a Schottky layer formed above the channel layer, a gate electrode formed on the Schottky layer, Ohmic contact layers that are located above the Schottky layer with the gate electrode interposed therebetween and formed of InGaAs, and a source electrode and a drain electrode that are formed on the Ohmic contact layers. The source electrode, the drain electrode and the gate electrode have a layered structure in which their corresponding layers are formed of the same material, a lowermost layer is a WSi layer and a layer containing Al is provided above the lowermost layer. A field effect transistor that has an electrode resistance equivalent to a conventional level and can reduce a cost of manufacturing a field effect transistor and a method for manufacturing the same are provided.

摘要翻译： 根据本发明的场效应晶体管包括形成在半绝缘衬底上的沟道层，形成在沟道层上方的肖特基层，形成在肖特基层上的栅电极，位于肖特基层上方的欧姆接触层， 介于其间并由InGaAs形成的栅电极以及形成在欧姆接触层上的源电极和漏电极。 源电极，漏电极和栅电极具有层叠结构，其相应的层由相同的材料形成，最下层是WSi层，并且在最下层上设置含有Al的层。 提供具有等同于常规水平的电极电阻并且可以降低制造场效应晶体管的成本的场效应晶体管及其制造方法。

公开(公告)号：US06967360B2

公开(公告)日：2005-11-22

申请号：US10617793

申请日：2003-07-14

申请人： Yoshiharu Anda ,  Akiyoshi Tamura

发明人： Yoshiharu Anda ,  Akiyoshi Tamura

IPC分类号： H01L21/28 ,  H01L21/335 ,  H01L21/338 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01L31/0328

CPC分类号： H01L29/66462 ,  H01L29/475 ,  H01L29/7784

摘要： A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件具有半绝缘GaAs衬底310，形成在半绝缘GaAs衬底310上的GaAs缓冲层321，AlGaAs缓冲层322，沟道层323，间隔层324，载流子供应层325， 间隔层326，由未掺杂的In 0.48 Ga 0.52 P材料构成的肖特基层327和n + 栅电极330形成在肖特基层327上，由LaB 6构成，与肖特基层327具有肖特基接触，并且欧姆电极340形成在第n + +型GaAs覆盖层328。

公开(公告)号：US5942772A

公开(公告)日：1999-08-24

申请号：US44845

申请日：1998-03-20

申请人： Katsunori Nishii ,  Mitsuru Nishitsuji ,  Takahiro Yokoyama ,  Akiyoshi Tamura

发明人： Katsunori Nishii ,  Mitsuru Nishitsuji ,  Takahiro Yokoyama ,  Akiyoshi Tamura

IPC分类号： H01L29/812 ,  H01L21/335 ,  H01L21/338 ,  H01L21/76 ,  H01L29/10 ,  H01L29/778 ,  H01L29/80 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/109 ,  H01L31/074

CPC分类号： H01L29/66446 ,  H01L21/7605 ,  H01L29/1029 ,  H01L29/7783 ,  H01L29/802

摘要： A heterojunction epitaxial layer, including a first semiconductor layer containing Al and having a thickness of 50 nm or less and a second semiconductor layer different in composition from the first semiconductor layer, is formed on a substrate composed of semi-insulating GaAs. A gate electrode is formed on a specified region of the top surface of the heterojunction epitaxial layer. The source/drain formation regions of the heterojunction epitaxial layer are provided with respective high-concentration N-type impurity diffusion regions, on which respective ohmic electrodes are formed.

摘要翻译： 在由半绝缘GaAs构成的衬底上形成异质结外延层，其包含含有Al且厚度为50nm以下的第一半导体层和与第一半导体层的组成不同的第二半导体层。 栅电极形成在异质结外延层的顶表面的特定区域上。 异质结外延层的源极/漏极形成区域设置有各自形成有各自的欧姆电极的高浓度N型杂质扩散区域。

公开(公告)号：US20060076585A1

公开(公告)日：2006-04-13

申请号：US11234172

申请日：2005-09-26

申请人： Yoshiaki Kato ,  Yoshiharu Anda ,  Akiyoshi Tamura

发明人： Yoshiaki Kato ,  Yoshiharu Anda ,  Akiyoshi Tamura

IPC分类号： H01L31/112

CPC分类号： H01L27/0605 ,  H01L27/0629

摘要： An object of the present invention is to provide a semiconductor resistor that allows improvement in saturation voltage characteristics and a method for manufacturing the same. The semiconductor resistor of the present invention is formed on the substrate on which a GaAs FET is formed. The GaAs FET includes: a channel layer; a Schottky layer formed on the channel layer and made of undoped InGaP; and a contact layer formed on the Schottky layer. The semiconductor resistor includes: a contact layer including a part of the contact layer isolated from the GaAs FET; an active region including a part of the Schottky layer and a part of the channel layer, both of which are isolated from the GaAs FET; and two ohmic electrodes formed on the contact layer, and the Schottky layer isolated from the GaAs FET is exposed in an area between the two ohmic electrodes.

摘要翻译： 本发明的一个目的是提供一种允许提高饱和电压特性的半导体电阻器及其制造方法。 本发明的半导体电阻器形成在其上形成有GaAs FET的基板上。 GaAs FET包括：沟道层; 形成在沟道层上并由未掺杂的InGaP制成的肖特基层; 以及形成在肖特基层上的接触层。 半导体电阻器包括：接触层，其包括与GaAs FET隔离的部分接触层; 包括肖特基层的一部分和沟道层的一部分的有源区域，两者都与GaAs FET隔离; 并且形成在接触层上的两个欧姆电极，并且从GaAs FET隔离的肖特基层暴露在两个欧姆电极之间的区域中。

公开(公告)号：US20050121695A1

公开(公告)日：2005-06-09

申请号：US11032164

申请日：2005-01-11

申请人： Yoshiharu Anda ,  Akiyoshi Tamura

发明人： Yoshiharu Anda ,  Akiyoshi Tamura

IPC分类号： H01L21/28 ,  H01L21/335 ,  H01L21/338 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01L31/072 ,  H01L29/739

CPC分类号： H01L29/66462 ,  H01L29/475 ,  H01L29/7784

摘要： A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件具有半绝缘GaAs衬底310，形成在半绝缘GaAs衬底310上的GaAs缓冲层321，AlGaAs缓冲层322，沟道层323，间隔层324，载流子供应层325， 间隔层326，由未掺杂的In 0.48 Ga 0.52 P材料构成的肖特基层327和n + 栅电极330形成在肖特基层327上，由LaB 6构成，与肖特基层327具有肖特基接触，并且欧姆电极340形成在第n + +型GaAs覆盖层328。

公开(公告)号：US07495268B2

公开(公告)日：2009-02-24

申请号：US11757533

申请日：2007-06-04

申请人： Yoshiaki Kato ,  Yoshiharu Anda ,  Akiyoshi Tamura

发明人： Yoshiaki Kato ,  Yoshiharu Anda ,  Akiyoshi Tamura

IPC分类号： H01L29/812

CPC分类号： H01L29/8128 ,  H01L29/42316 ,  H01L29/66863 ,  H01L29/778

摘要： A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.

摘要翻译： 根据本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的沟道层; 在沟道层上形成的施主层; 形成在供体层上的第一肖特基层; 形成在第一肖特基层上的第二肖特基层; 形成在所述第一肖特基层上以与所述第一肖特基层形成肖特基势垒结的第一栅电极; 第一源电极和第一漏电极，其形成为夹着所述第一栅电极并电连接到所述沟道层; 第二栅电极，形成在所述第二肖特基层上，并且由与所述第一栅电极不同的材料制成，以与所述第二肖特基层形成肖特基势垒结; 以及第二源电极和第二漏电极，其形成为夹着所述第二栅极并电连接到所述沟道层。

公开(公告)号：US20060281237A1

公开(公告)日：2006-12-14

申请号：US11382991

申请日：2006-05-12

申请人： Akiyoshi Kudo ,  Yoshiharu Anda ,  Akiyoshi Tamura

发明人： Akiyoshi Kudo ,  Yoshiharu Anda ,  Akiyoshi Tamura

IPC分类号： H01L21/338

CPC分类号： H01L29/207 ,  H01L29/66924 ,  H01L29/808

摘要： A method of manufacturing a junction field-effect transistor which controls variations of p-type impurities in a gate region and obtains a favorable PN junction characteristic includes: depositing ZnO in a thin layer by a sputtering method on a surface of a region in which a gate electrode of an n+-AlGaAs layer formed on a GaAs substrate is to be formed; forming a p-type gate region by solid-phase diffusion which is performed by processes of rapid heating and fast cooling; removing the ZnO with wet etching using tartaric acid and the like so as to expose the p-type gate region; and forming the gate electrode on the exposed p-type gate region.

摘要翻译： 一种控制栅极区域中的p型杂质的变化并获得良好的PN结特性的结型场效应晶体管的制造方法包括：在溅射法的薄层中，在 要形成在GaAs衬底上形成的n + + / - AlGaAs层的栅电极; 通过快速加热和快速冷却过程进行的固相扩散形成p型栅极区; 用酒石酸等湿法蚀刻除去ZnO，露出p型栅区; 以及在暴露的p型栅极区上形成栅电极。

公开(公告)号：US20060273396A1

公开(公告)日：2006-12-07

申请号：US11383561

申请日：2006-05-16

申请人： Yoshiharu Anda ,  Akiyoshi Tamura ,  Hirotada Taniuchi

发明人： Yoshiharu Anda ,  Akiyoshi Tamura ,  Hirotada Taniuchi

IPC分类号： H01L27/12

CPC分类号： H01L29/7783 ,  H01L21/7605 ,  H01L27/0605 ,  H01L29/8605

摘要： The present invention aims to provide a semiconductor device that can improve an element isolation breakdown voltage, which includes a semiconductor resistor using an InGaP layer as a semiconductor layer exposed on a surface. The present invention includes: an FET having a channel layer and a schottky layer which is made of undoped InGaP and is formed on the channel layer; and a semiconductor resistor having a part of the schottky layer and channel layer which are isolated from the FET by the element isolation region. The FET and semiconductor resistor are formed on a substrate, and the schottky layer is removed in the element isolation region.

摘要翻译： 本发明的目的在于提供一种能够提高元件隔离击穿电压的半导体器件，该半导体器件包括使用InGaP层作为在表面上露出的半导体层的半导体电阻。 本发明包括：具有沟道层和肖特基层的FET，其由未掺杂的InGaP制成并形成在沟道层上; 以及具有通过元件隔离区域与FET隔离的肖特基层和沟道层的一部分的半导体电阻器。 FET和半导体电阻器形成在衬底上，并且在元件隔离区域中去除肖特基层。

公开(公告)号：US07144765B2

公开(公告)日：2006-12-05

申请号：US11032164

申请日：2005-01-11

申请人： Yoshiharu Anda ,  Akiyoshi Tamura

发明人： Yoshiharu Anda ,  Akiyoshi Tamura

IPC分类号： H01L21/338

CPC分类号： H01L29/66462 ,  H01L29/475 ,  H01L29/7784

摘要： A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件具有半绝缘GaAs衬底310，形成在半绝缘GaAs衬底310上的GaAs缓冲层321，AlGaAs缓冲层322，沟道层323，间隔层324，载流子供应层325， 间隔层326，由未掺杂的In 0.48 Ga 0.52 P材料构成的肖特基层327和n + 栅电极330形成在肖特基层327上，由LaB 6构成，与肖特基层327具有肖特基接触，并且欧姆电极340形成在第n + +型GaAs覆盖层328。

公开(公告)号：US08017975B2

公开(公告)日：2011-09-13

申请号：US12400376

申请日：2009-03-09

申请人： Keiichi Murayama ,  Akiyoshi Tamura ,  Hirotaka Miyamoto ,  Kenichi Miyajima

发明人： Keiichi Murayama ,  Akiyoshi Tamura ,  Hirotaka Miyamoto ,  Kenichi Miyajima

IPC分类号： H01L29/66

CPC分类号： H01L27/0623 ,  H01L21/8248 ,  H01L27/0605 ,  H01L29/7371 ,  H01L29/802

摘要： A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.

摘要翻译： 半导体器件和制造方法满足HBT和HFET两者的折衷特性优点。 该半导体器件是HBT和HFET集成电路。 HBT包括依次堆叠的子集电极层，GaAs集电极层，GaAs基极层和InGaP发射极层。 子集电极层包括GaAs外部副集电极区域和设置在GaAs外部子集电极区域上的GaAs内部子集电极区域。 在GaAs外部副集电极区域上分别形成台状集电体部和集电极。 HFET包括GaAs覆盖层，源电极和漏电极。 GaAs覆盖层包括GaAs外部副集电极区域的一部分。 源电极和漏极形成在GaAs盖层上。