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公开(公告)号：US20100327261A1
公开(公告)日：2010-12-30
申请号：US12876922
申请日：2010-09-07
IPC分类号： H01L29/775 , H01L29/20
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02573 , H01L21/0262 , H01L29/267 , H01L29/66431
摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译： 本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。 一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。 该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。
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2.发明授权公开(公告)号：US07791063B2
公开(公告)日：2010-09-07
申请号：US11847780
申请日：2007-08-30
IPC分类号： H01L29/205 , H01L21/20
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02573 , H01L21/0262 , H01L29/267 , H01L29/66431
摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译： 本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。 一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。 该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。
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3.发明授权公开(公告)号：US08217383B2
公开(公告)日：2012-07-10
申请号：US12876922
申请日：2010-09-07
IPC分类号： H01L29/775 , H01L29/20
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02573 , H01L21/0262 , H01L29/267 , H01L29/66431
摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译： 本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。 一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。 该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。
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4.发明申请公开(公告)号：US20090057648A1
公开(公告)日：2009-03-05
申请号：US11847780
申请日：2007-08-30
IPC分类号： H01L29/205 , H01L21/20
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02573 , H01L21/0262 , H01L29/267 , H01L29/66431
摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译： 本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。 一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。 该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。
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5.发明授权Dislocation removal from a group III-V film grown on a semiconductor substrate 有权从在半导体衬底上生长的III-V族膜剥离公开(公告)号：US07863710B2
公开(公告)日：2011-01-04
申请号：US12032579
申请日：2008-02-15
IPC分类号： H01L29/20
CPC分类号： H01L21/02664 , H01L21/02381 , H01L21/02433 , H01L21/02461 , H01L21/02463 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02686 , H01L21/268
摘要： Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.
摘要翻译： 通常描述从在半导体衬底上生长的III-V族膜脱离脱落。 在一个示例中，一种装置包括半导体衬底，包括外延耦合到半导体衬底的III-V族半导体材料的缓冲膜，其中缓冲膜包括通过激光脉冲照射熔化的材料并重结晶以基本上从缓冲器中去除位错或缺陷 膜，以及在所述缓冲膜上外延生长的第一半导体膜，其中在所述半导体衬底和所述第一半导体膜之间存在晶格失配。
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6.发明申请DISLOCATION REMOVAL FROM A GROUP III-V FILM GROWN ON A SEMICONDUCTOR SUBSTRATE 有权在半导体基板上形成的III-V族薄膜的分离去除公开(公告)号：US20090206324A1
公开(公告)日：2009-08-20
申请号：US12032579
申请日：2008-02-15
IPC分类号： H01L29/205 , H01L21/268
CPC分类号： H01L21/02664 , H01L21/02381 , H01L21/02433 , H01L21/02461 , H01L21/02463 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02686 , H01L21/268
摘要： Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.
摘要翻译： 通常描述从在半导体衬底上生长的III-V族膜脱离脱落。 在一个示例中，一种装置包括半导体衬底，包括外延耦合到半导体衬底的III-V族半导体材料的缓冲膜，其中缓冲膜包括通过激光脉冲照射熔化的材料并重结晶以基本上从缓冲器中去除位错或缺陷 膜，以及在所述缓冲膜上外延生长的第一半导体膜，其中在所述半导体衬底和所述第一半导体膜之间存在晶格失配。
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公开(公告)号：US20140291615A1
公开(公告)日：2014-10-02
申请号：US14302371
申请日：2014-06-11
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L29/15
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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公开(公告)号：US20120199813A1
公开(公告)日：2012-08-09
申请号：US13450359
申请日：2012-04-18
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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9.发明授权Thin transition layer between a group III-V substrate and a high-k gate dielectric layer 有权III-V族衬底和高k栅介质层之间的薄过渡层公开(公告)号：US07879739B2
公开(公告)日：2011-02-01
申请号：US11382428
申请日：2006-05-09
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31616 , H01L21/02178 , H01L21/0228 , H01L21/02304 , H01L21/28264 , H01L29/513 , H01L29/78
摘要： Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on the substrate from which the oxide was removed. The high-k dielectric layer may then be formed, resulting in a thin transition layer between the substrate and high-k dielectric layer and substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer.
摘要翻译： 本发明的实施例提供了在基板和高k电介质层之间基本上不具有III-V族衬底的氧化物的III-V族衬底上形成高k电介质层的方法。 氧化物可以从衬底去除。 有机金属化合物可以在去除氧化物的基底上形成覆盖层。 然后可以形成高k电介质层，导致衬底和高k电介质层之间的薄过渡层，并且在衬底和高k电介质层之间基本上不存在III-V族衬底的氧化物。
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公开(公告)号：US20080116485A1
公开(公告)日：2008-05-22
申请号：US11560494
申请日：2006-11-16
IPC分类号： H01L27/092
CPC分类号： H01L27/0605 , H01L21/8252 , H01L27/092
摘要： A group III-V material CMOS device may have NMOS and PMOS portions that are substantially the same through several of their layers. This may make the CMOS device easy to make and prevent coefficient of thermal expansion mismatches between the NMOS and PMOS portions.
摘要翻译： III-V族材料CMOS器件可以具有通过它们的几个层基本上相同的NMOS和PMOS部分。 这可能使CMOS器件易于制造并且防止NMOS和PMOS部分之间的热膨胀失配系数。
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