公开(公告)号：US5187683A

公开(公告)日：1993-02-16

申请号：US576307

申请日：1990-08-31

申请人： Manzur Gill ,  Sung-Wei Lin ,  Sebastiano D'Arrigo

发明人： Manzur Gill ,  Sung-Wei Lin ,  Sebastiano D'Arrigo

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/08 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115

CPC分类号： G11C16/08 ,  G11C16/10

摘要： A method is described for programming a semiconductor array of EEPROM cells. A selected cell is connected, by definition, to a selected source-column line, a selected drain-column line and a selected wordline. Each deselected memory cell in the array is connected to a deselected source-column line, a deselected drain-column line and/or a deselected wordline. The method includes preselecting first, second, third, fourth and fifth programming voltages such that the second programming voltage is more positive than the first programming voltage and such that the third, fourth and fifth programming voltages are intermediate between the first and second programming voltages. The first programming voltage is applied at least to a selected column line and to each of the same-type deselected column lines. The third programming voltage is applied to the selected wordline and the fourth programming voltage is applied to each deselected wordline. After a pre-charge time interval, the fifth programming voltage is applied to each same-type deselected column line and, after an optional additional pre-charge time interval, the second programming voltage is applied to the selected wordline. After a program time interval, the third programming voltage is applied to the selected wordline and, after an optional discharge time interval, the first programming voltage is applied to each same-type deselected column line. Each deselected wordline is maintained at the fourth programming voltage for an additional discharge time interval. The third, fourth and fifth programming voltages may have the same value.

摘要翻译： 描述了一种用于编程EEPROM单元的半导体阵列的方法。 根据定义，所选择的单元格连接到所选择的源列行，所选的排列列线和所选择的字线。 阵列中的每个取消选择的存储单元连接到未选择的源 - 列线，取消选择的漏 - 列线和/或未选择的字线。 该方法包括预选第一，第二，第三，第四和第五编程电压，使得第二编程电压比第一编程电压更正，并且使得第三，第四和第五编程电压在第一和第二编程电压之间。 至少将第一编程电压施加到所选择的列线和每个相同类型的未选择的列线。 将第三编程电压施加到所选择的字线，并且将第四编程电压施加到每个取消选择的字线。 在预充电时间间隔之后，将第五编程电压施加到每个相同类型的未选择的列线，并且在可选的附加预充电时间间隔之后，将第二编程电压施加到所选择的字线。 在编程时间间隔之后，将第三编程电压施加到所选择的字线，并且在可选的放电时间间隔之后，将第一编程电压施加到每个相同类型的未选择的列线。 每个取消选择的字线保持在第四个编程电压下一个额外的放电时间间隔。 第三，第四和第五编程电压可以具有相同的值。

公开(公告)号：US5168335A

公开(公告)日：1992-12-01

申请号：US741975

申请日：1991-08-06

申请人： Iano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

发明人： Iano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L29/7883

摘要： A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective source regions (30a, 30b), a shared drain region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) that controls the conductance of a respective subchannel region (74a, 74b) and may be programmed through Fowler-Nordheim electron tunneling through a respective tunnel oxide window (40a, 40b) from a respective source region (30a, 30b). A field plate conductor (40a) controls the conductance of respective subchannel regions (70a, 70b) within each channel region (38a, 38b). A word line or control gate conductor (62) is insulatively disposed adjacent respective third, remaining channel subregions (53a, 53b) and further is disposed insulatively adjacent the floating gates (46a, 46b) to program or erase them.

摘要翻译： 在半导体层（10）的表面上形成一对电可擦除的电可编程存储单元，并且包括各自的源极区（30a，30b），共用漏极区（28）和各个沟道区（38a，38b）。 每个单元具有控制相应子通道区域（74a，74b）的电导的浮栅导体（46a，46b），并且可以通过Fowler-Nordheim电子隧穿通过相应的隧道氧化物窗（40a，40b）从相应的 源区域（30a，30b）。 场板导体（40a）控制每个通道区域（38a，38b）内各个子通道区域（70a，70b）的电导。 字线或控制栅极导体（62）被绝对地设置在相邻的第三剩余通道子区域（53a，53b）附近，并且还与浮动栅极（46a，46b）绝缘地设置以编程或擦除它们。

公开(公告)号：US5156991A

公开(公告)日：1992-10-20

申请号：US648087

申请日：1991-01-31

申请人： Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

发明人： Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L29/7883 ,  Y10S438/981

摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized.

摘要翻译： 使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了 易于制造和减小电池尺寸。 位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 隧道窗口提供的编程和擦除靠近或高于源的通道侧。 窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。 通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。 在优选实施例中，字线之间的隔离也是厚氧化物，进一步提高了耦合比。 可以选择位线和字线间距来获得最佳间距或宽高比。 位线到基板电容最小化。

公开(公告)号：US5218568A

公开(公告)日：1993-06-08

申请号：US809462

申请日：1991-12-17

申请人： Sung-Wei Lin ,  Manzur Gill ,  Inn K. Lee

发明人： Sung-Wei Lin ,  Manzur Gill ,  Inn K. Lee

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： An electrically-erasable, electrically-programmable read-only memory cell 10 is formed at a face of a layer of semiconductor 30 of a first conductivity type. A first source/drain region 16 and a second source/drain region 20 are formed in the face of layer of semiconductor 30 of a second conductivity type opposite the first conductivity type and spaced by a first channel area 50. A third source/drain region 18 is formed in the face of semiconductor layer 30 of the second conductivity type spaced from second source/drain region 20 by a second channel area 52. A thick insulator region 44 is formed adjacent at least a portion of second source/drain region 20 and includes a lateral margin of sloped thickness overlying a corresponding lateral margin of second source/drain region 20. The corresponding lateral margin of second source/drain region 20 has a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of thick insulator region 44. A differentially grown insulator region 54 overlies second source/drain region 20 and includes a lateral margin of sloped thickness. A thin insulator tunneling window 62 overlies an area 60 of second source/drain region 20, tunneling window 62 formed between and spacing the lateral margin of the thick insulator region 44 and the lateral margin of differentially grown insulator region 54. A floating gate conductor 26 is disposed adjacent tunneling window 62 and insulatively adjacent second channel area 52. A control gate conductor 28 is disposed insulatively adjacent floating gate conductor 28. A gate conductor 24 is disposed insulatively adjacent first channel area 50.

摘要翻译： 电可擦除的电可编程只读存储单元10形成在第一导电类型的半导体层30的表面。 第一源极/漏极区域16和第二源极/漏极区域20形成在与第一导电类型相反并且由第一沟道区域50间隔开的第二导电类型的半导体层30的表面中。第三源极/漏极区域 18形成在第二导电类型的半导体层30的表面上，第二导电类型的第二导电类型与第二源极/漏极区域20间隔开第二沟道区域52.邻近第二源极/漏极区域20的至少一部分形成厚的绝缘体区域44， 包括覆盖第二源极/漏极区域20的相应横向边缘的倾斜厚度的横向边缘。第二源极/漏极区域20的对应横向边缘具有与厚度绝缘体的上覆侧边缘的倾斜厚度成正比的渐变掺杂剂浓度 差分生长的绝缘体区域54覆盖第二源极/漏极区域20并且包括倾斜厚度的侧向边缘。 薄的绝缘体隧道窗口62覆盖在第二源极/漏极区域20的区域60之间，形成在厚绝缘体区域44的侧边缘之间并且间隔着厚的绝缘体区域44的侧边缘和差分生长的绝缘体区域54的横向边缘之间的隧道窗口62.浮动栅极导体26 被布置在相邻的隧道窗口62和绝对相邻的第二通道区域52处。控制栅极导体28被隔离地邻近浮置栅极导体28设置。栅极导体24与第一沟道区域50绝缘地邻近设置。

公开(公告)号：US5155055A

公开(公告)日：1992-10-13

申请号：US685358

申请日：1991-04-15

申请人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

发明人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L29/7883

摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

摘要翻译： 使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口 通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。 在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。 隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

公开(公告)号：US5008721A

公开(公告)日：1991-04-16

申请号：US494042

申请日：1990-03-15

申请人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

发明人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L29/7883 ,  Y10S257/903

摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

摘要翻译： 使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口 通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。 在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。 隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

公开(公告)号：US5523249A

公开(公告)日：1996-06-04

申请号：US364529

申请日：1994-12-23

申请人： Manzur Gill ,  David J. McElroy ,  Sung-Wei Lin ,  Inn K. Lee

发明人： Manzur Gill ,  David J. McElroy ,  Sung-Wei Lin ,  Inn K. Lee

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17 ). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.

摘要翻译： 在半导体衬底（22）的表面上成对地形成电可擦除的电可编程的只读存储单元阵列。 每个存储单元包括源极区域（11）和漏极区域（12），其间具有相应的沟道区域。 福勒 - 诺德海姆隧道窗口（13a）位于连接到源（11）的源极线（17）上。 浮动门（13）包括隧道窗部分。 控制栅极（14）设置在浮置栅极（13）上，由中间层间电介质（27）绝缘。 浮动栅极（13）和控制栅极（14）包括通道部分（Ch）。 通道部分（Ch）用作源（11）和漏极（12）区域的自对准注入掩模，使得沟道结边缘与通道部分（Ch）的相应边缘对齐。 存储单元通过从通道的热载流子注入到浮动栅极（13）进行编程，并由Fowler-Nordheim从浮动栅极（13）通过隧道窗口（13a）到源极线（17）的隧道擦除， 。 单元的程序和擦除区域在物理上彼此分离，并且这些区域中的每一个的特性，包括氧化物可以彼此独立地最优化。

公开(公告)号：US5017980A

公开(公告)日：1991-05-21

申请号：US494051

申请日：1990-03-15

申请人： Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

发明人： Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L29/7883

摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between cells in the wordline direction is by a self-aligned implanted region, in this embodiment.

摘要翻译： 使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了 易于制造和减小电池尺寸。 位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由位于源的通道侧附近或上方的隧道窗口区域提供。 窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。 通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。 在本实施例中，字线方向上的单元之间的隔离是通过自对准注入区域。

公开(公告)号：US5177705A

公开(公告)日：1993-01-05

申请号：US402399

申请日：1989-09-05

申请人： David J. McElroy ,  Sebastiano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

发明人： David J. McElroy ,  Sebastiano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0425 ,  G11C16/10

摘要： A method is described for programming an array of EEPROM cells. Programming occurs through a Fowler-Nordheim tunnel window (34) between a source bitline (24) and a floating gate conductor (42) of a selected cell. The voltages applied to the control gate and to the source are selected to differ sufficiently to cause electrons to be drawn through the tunnel window (34) from the source region (24) to the floating gate conductor (42). The non-selected bitlines have a voltage impressed thereon that is of sufficient value to prevent inadvertent programming of cells in the selected row. The non-selected wordlines (48) have a voltage impressed thereon that is of sufficient value to prevent erasing of programmed non-selected cells.

摘要翻译： 描述了一种用于编程EEPROM单元阵列的方法。 编程通过位于选定单元的源位线（24）和浮动栅极导体（42）之间的Fowler-Nordheim隧道窗口（34）进行。 选择施加到控制栅极和源极的电压以使其不同以使得电子从源极区域（24）通过隧道窗口（34）从浮动栅极导体（42）拉出。 未选择的位线具有施加在其上的电压，其具有足够的值以防止所选行中的单元的无意编程。 未选择的字线（48）具有其上施加的电压，其具有足够的值以防止编程的未选择单元的擦除。

公开(公告)号：US5060195A

公开(公告)日：1991-10-22

申请号：US595521

申请日：1990-10-11

申请人： Manzur Gill ,  Sung-Wei Lin

发明人： Manzur Gill ,  Sung-Wei Lin

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7885

摘要： An electrically-erasable, electrically-programmable, read-only memory cell array is formed in pairs at a face of a semiconductor substrate (11). Each memory cell includes a source region (14a) and a shaped drain region (16), with at corresponding channel region (18a) in between. A Fowler-Nordheim tunnel window subregion (15a) of the source region (14a) is located opposite the channel (18a). A floating gate conductor (FG) includes a channel section (32a) and a tunnel window section (34a). The floating gate conductor is formed in two stages, the first stage forming the channel section (32a) from a first-level polysilicon (P1A). This floating gate channel section (32a/P1A) is used as a self-alignment implant mask for the source (14a) and drain (16) regions, such that the channel junction edges are aligned with the coresponding edges of the channel section. A control gate conductor (CG) is disposed over the floating gate conductor (FG), insulated by an intervening interlevel dielectric (ILD). The memory cell is programmed by hot carrier injection from the channel (18a) to the floating-gate channel section (32a), and erased by Fowler-Nordheim tunneling from the floating-gate tunnel window section (34a) to the tunnel window subregion (15a).

摘要翻译： 在半导体衬底（11）的表面成对地形成电可擦除的电可编程的只读存储单元阵列。 每个存储单元包括源极区域（14a）和形状的漏极区域（16），其间具有相应的沟道区域（18a）。 源区域（14a）的福勒 - 诺德海姆隧道窗口（15a）位于与通道（18a）相对的位置。 浮动栅极导体（FG）包括通道部分（32a）和隧道窗口部分（34a）。 浮栅导体形成为两级，第一级由第一级多晶硅（P1A）形成沟道段（32a）。 该浮动栅极沟道部分（32a / P1A）用作源极（14a）和漏极（16）区域的自对准注入掩模，使得沟道连接边缘与沟道部分的相应边缘对准。 控制栅极导体（CG）设置在浮动栅极导体（FG）上，由中间层间电介质（ILD）绝缘。 通过从信道（18a）到浮动栅极通道部分（32a）的热载流子注入来对存储器单元进行编程，并且通过Fowler-Nordheim从浮动栅极通道窗口部分（34a）向隧道窗口子区域（ 15a）。