公开(公告)号：US08686505B2

公开(公告)日：2014-04-01

申请号：US13560109

申请日：2012-07-27

申请人： Marc Strasser ,  Karl-Heinz Gebhardt ,  Ralf Rudolf ,  Lincoln O'Riain

发明人： Marc Strasser ,  Karl-Heinz Gebhardt ,  Ralf Rudolf ,  Lincoln O'Riain

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/301 ,  H01L21/335

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66681

摘要： A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.

摘要翻译： 一种方法产生半导体器件，其包括半导体本体，其上的电极以及将电极与半导体本体绝缘的绝缘结构。 半导体本体包括第一导电类型的第一接触区域，第二导电类型的体区域，第一导电类型的漂移区域和具有比漂移区域更高的最大掺杂浓度的第二接触区域。 绝缘结构包括形成第一水平界面的栅介质部分。 具有漂移区域并且具有第一最大垂直延伸部A场介电部分形成，漂移区域布置在主表面下方的第二和第三水平界面。 场介电部分的第二最大垂直延伸大于第一最大垂直延伸。 场电介质部分的第三最大垂直延伸大于第二最大垂直延伸。

公开(公告)号：US20140027848A1

公开(公告)日：2014-01-30

申请号：US13560109

申请日：2012-07-27

申请人： Marc Strasser ,  Karl-Heinz Gebhardt ,  Ralf Rudolf ,  Lincoln O'Riain

发明人： Marc Strasser ,  Karl-Heinz Gebhardt ,  Ralf Rudolf ,  Lincoln O'Riain

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66681

摘要： A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.

摘要翻译： 一种方法产生半导体器件，其包括半导体本体，其上的电极以及将电极与半导体本体绝缘的绝缘结构。 半导体本体包括第一导电类型的第一接触区域，第二导电类型的体区域，第一导电类型的漂移区域和具有比漂移区域更高的最大掺杂浓度的第二接触区域。 绝缘结构包括形成第一水平界面的栅介质部分。 具有漂移区域并且具有第一最大垂直延伸部A场介电部分形成，漂移区域布置在主表面下方的第二和第三水平界面。 场介电部分的第二最大垂直延伸大于第一最大垂直延伸。 场电介质部分的第三最大垂直延伸大于第二最大垂直延伸。

公开(公告)号：US20050095788A1

公开(公告)日：2005-05-05

申请号：US10966994

申请日：2004-10-15

申请人： Lincoln O'Riain ,  Jorg Radecker

发明人： Lincoln O'Riain ,  Jorg Radecker

IPC分类号： H01L21/762 ,  H01L29/94

CPC分类号： H01L21/76224

摘要： A method for encapsulating a filling in a trench of a semiconductor substrate includes providing a first barrier layer in a trench and a second barrier layer disposed above the first barrier layer. The trench is filled with a filling, which is subsequently etched back in an upper trench section, so that a hole is produced and a filling residue remains in a lower trench section. Subsequently, a non-conformal cover layer is provided in an upper trench section, so that the cover layer of a bottom region has a first thickness greater than a second thickness of a wall region of the cover layer. The cover layer and the second barrier layer are isotropically etched-back and removed from the upper trench section, and the first barrier layer remains. The bottom region remains covered resulting in the filling residue being encapsulated by the first barrier layer and the residual cover layer.

摘要翻译： 一种用于将填充物封装在半导体衬底的沟槽中的方法包括在沟槽中提供第一阻挡层，以及设置在第一阻挡层上方的第二阻挡层。 沟槽填充有填充物，其随后在上沟槽部分中被回蚀，使得产生孔并且填充残留物残留在下沟槽部分中。 随后，在上沟槽部分中设置非保形覆盖层，使得底部区域的覆盖层具有大于覆盖层的壁区域的第二厚度的第一厚度。 覆盖层和第二阻挡层被从上沟槽部分各向同性地回蚀和去除，并且第一阻挡层保留。 底部区域保持覆盖，导致填充残余物被第一阻挡层和残余覆盖层封装。

公开(公告)号：US06908831B2

公开(公告)日：2005-06-21

申请号：US10966994

申请日：2004-10-15

申请人： Lincoln O'Riain ,  Jörg Radecker

发明人： Lincoln O'Riain ,  Jörg Radecker

IPC分类号： H01L21/762 ,  H01L29/94

CPC分类号： H01L21/76224

摘要： A method for encapsulating a filling in a trench of a semiconductor substrate includes providing a first barrier layer in a trench and a second barrier layer disposed above the first barrier layer. The trench is filled with a filling, which is subsequently etched back in an upper trench section, so that a hole is produced and a filling residue remains in a lower trench section. Subsequently, a non-conformal cover layer is provided in an upper trench section, so that the cover layer of a bottom region has a first thickness greater than a second thickness of a wall region of the cover layer. The cover layer and the second barrier layer are isotropically etched-back and removed from the upper trench section, and the first barrier layer remains. The bottom region remains covered resulting in the filling residue being encapsulated by the first barrier layer and the residual cover layer.

摘要翻译： 一种用于将填充物封装在半导体衬底的沟槽中的方法包括在沟槽中提供第一阻挡层，以及设置在第一阻挡层上方的第二阻挡层。 沟槽填充有填充物，其随后在上沟槽部分中被回蚀，使得产生孔并且填充残留物残留在下沟槽部分中。 随后，在上沟槽部分中设置非保形覆盖层，使得底部区域的覆盖层具有大于覆盖层的壁区域的第二厚度的第一厚度。 覆盖层和第二阻挡层被从上沟槽部分各向同性地回蚀和去除，并且第一阻挡层保留。 底部区域保持覆盖，导致填充残余物被第一阻挡层和残余覆盖层封装。

公开(公告)号：US08115279B2

公开(公告)日：2012-02-14

申请号：US12769271

申请日：2010-04-28

申请人： Armin Tilke ,  Cajetan Wagner ,  Lincoln O'Riain

发明人： Armin Tilke ,  Cajetan Wagner ,  Lincoln O'Riain

IPC分类号： H01L29/06

CPC分类号： H01L21/76264 ,  H01L21/743

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.

摘要翻译： 公开了半导体器件及其制造方法。 在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。 隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。 扩散限制结构设置在隔离环结构的内部区域内。 导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。 扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

公开(公告)号：US07749859B2

公开(公告)日：2010-07-06

申请号：US11771583

申请日：2007-06-29

申请人： Armin Tilke ,  Cajetan Wagner ,  Lincoln O'Riain

发明人： Armin Tilke ,  Cajetan Wagner ,  Lincoln O'Riain

IPC分类号： H01L29/00

CPC分类号： H01L21/76264 ,  H01L21/743

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.

摘要翻译： 公开了半导体器件及其制造方法。 在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。 隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。 扩散限制结构设置在隔离环结构的内部区域内。 导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。 扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

公开(公告)号：US20110309441A1

公开(公告)日：2011-12-22

申请号：US12819856

申请日：2010-06-21

申请人： Matthias Stecher ,  Hans Weber ,  Lincoln O'Riain ,  Birgit von Ehrenwall

发明人： Matthias Stecher ,  Hans Weber ,  Lincoln O'Riain ,  Birgit von Ehrenwall

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L21/76

CPC分类号： H01L27/1207 ,  H01L21/187 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0251 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/66681 ,  H01L29/7816

摘要： An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.

摘要翻译： 提供集成半导体器件。 集成半导体器件具有第二导电类型的第一半导体区域，与第一半导体区域形成pn结的第一导电类型的第二半导体区域，布置在第二导电类型的第二导电类型的非单晶半导体层 半导体区域，布置在非单晶半导体层上的第一导电类型的第一阱和至少一个第二阱以及使第一阱与至少一个第二阱和非单晶半导体层绝缘的绝缘结构。 此外，提供了一种用于形成半导体器件的方法。

公开(公告)号：US08749018B2

公开(公告)日：2014-06-10

申请号：US12819856

申请日：2010-06-21

申请人： Matthias Stecher ,  Hans Weber ,  Lincoln O'Riain ,  Birgit von Ehrenwall

发明人： Matthias Stecher ,  Hans Weber ,  Lincoln O'Riain ,  Birgit von Ehrenwall

IPC分类号： H01L21/70

CPC分类号： H01L27/1207 ,  H01L21/187 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0251 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/66681 ,  H01L29/7816

摘要： An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.

摘要翻译： 提供集成半导体器件。 集成半导体器件具有第二导电类型的第一半导体区域，与第一半导体区域形成pn结的第一导电类型的第二半导体区域，布置在第二导电类型的第二导电类型的非单晶半导体层 半导体区域，布置在非单晶半导体层上的第一导电类型的第一阱和至少一个第二阱以及使第一阱与至少一个第二阱和非单晶半导体层绝缘的绝缘结构。 此外，提供了一种用于形成半导体器件的方法。

公开(公告)号：US20100207238A1

公开(公告)日：2010-08-19

申请号：US12769271

申请日：2010-04-28

申请人： Armin Tilke ,  Cajetan Wagner ,  Lincoln O'Riain

发明人： Armin Tilke ,  Cajetan Wagner ,  Lincoln O'Riain

IPC分类号： H01L29/06

CPC分类号： H01L21/76264 ,  H01L21/743

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.

摘要翻译： 公开了半导体器件及其制造方法。 在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。 隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。 扩散限制结构设置在隔离环结构的内部区域内。 导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。 扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

公开(公告)号：US20090001502A1

公开(公告)日：2009-01-01

申请号：US11771583

申请日：2007-06-29

申请人： Armin Tilke ,  Cajetan Wagner ,  Lincoln O'Riain

发明人： Armin Tilke ,  Cajetan Wagner ,  Lincoln O'Riain

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L21/76264 ,  H01L21/743

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.

摘要翻译： 公开了半导体器件及其制造方法。 在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。 隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。 扩散限制结构设置在隔离环结构的内部区域内。 导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。 扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。