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公开(公告)号：US07196537B2
公开(公告)日：2007-03-27
申请号：US11092963
申请日：2005-03-30
IPC分类号： G01R31/26
CPC分类号： G11C29/1201 , G01R31/275 , G01R31/2884 , G11C29/48 , G11C29/50 , G11C2029/5002
摘要： An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.
摘要翻译： 集成电路包括电路部件，第一控制电路和可切换电阻网络。 输入电压被馈送到输入侧的电路部件。 由第一控制电路产生的控制信号被馈送到电路部件的控制端。 利用可切换电阻网络，第一电阻或第二电阻连接在电路部件的输出端和集成电路的输出端之间，以在电路部件的输入侧和输出端之间产生电压降。 集成电路使得可以以取决于控制信号的方式在电路部件的输出端产生电流以及在电路部件的输入侧和输出端子之间落下的电压。 集成电路的晶体管的特性曲线族由集成电路确定。
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公开(公告)号：US07203883B2
公开(公告)日：2007-04-10
申请号：US11086655
申请日：2005-03-23
IPC分类号： G06F11/00
CPC分类号： G11C29/50012 , G01R31/3016 , G11C29/02
摘要： An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.
摘要翻译： 可以在正常运行状态和测试运行状态下运行的集成半导体存储器包括具有用于施加输入信号的输入端的电流脉冲电路。 电流脉冲电路经由用于承载电流的互连件连接到输出端子。 在测试操作状态下，当前脉冲电路在第一测试周期中产生具有第一预定持续时间的至少一个第一电流脉冲，以及在随后的第二测试周期中具有第二未知持续时间的至少一个第二电流脉冲。 除了在正常操作状态下在互连上流动的第一电流之外，第二电流在第一测试周期期间在互连上流动，并且第三电流在测试操作状态期间在第二测试周期期间流动。
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公开(公告)号：US07365554B2
公开(公告)日：2008-04-29
申请号：US11092885
申请日：2005-03-29
IPC分类号： G01R31/02
CPC分类号： G11C5/143 , G01R19/16552 , G11C11/401 , G11C11/4074 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C2029/5004
摘要： An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.
摘要翻译： 集成电路包括具有用于施加参考电压的第一输入端子的电流发生器电路和用于施加由外部施加的电源电压内部由电压发生器电路产生的输入电压的第二输入端子。 电流发生器电路通过互连连接到输出端子。 在集成电路的测试操作状态下，第一电流在互连上流动。 电流发生器电路在随后的第二测试周期中在测试操作状态的第一测试周期和第二部分电流中产生第一部分电流。 部分电流各自叠加在互连上的第一电流上。 因此，在测试操作状态期间，输出端子发生三个电流。 电流发生器电路的内部产生的输入电压由三个电流和参考电压确定。
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公开(公告)号：US07224627B2
公开(公告)日：2007-05-29
申请号：US11100617
申请日：2005-04-07
IPC分类号： G11C7/00
CPC分类号： G11C29/12005 , G11C29/12
摘要： Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.
摘要翻译： 集成半导体电路，特别是动态随机存取存储器包括用于从外部施加的电源电压产生内部电压电平的多个发生器电路。 在测试期间，内部电压电平由发生器电路输出端产生的输出电压改变为外部施加的测试电压。 如果测试电压超出公差范围，则半导体电路可能被破坏。 与发生器电路并联连接的保护电路限制输出电压。
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公开(公告)号：US20050229054A1
公开(公告)日：2005-10-13
申请号：US11086655
申请日：2005-03-23
CPC分类号： G11C29/50012 , G01R31/3016 , G11C29/02
摘要： An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.
摘要翻译： 可以在正常运行状态和测试运行状态下运行的集成半导体存储器包括具有用于施加输入信号的输入端的电流脉冲电路。 电流脉冲电路经由用于承载电流的互连件连接到输出端子。 在测试操作状态下，当前脉冲电路在第一测试周期中产生具有第一预定持续时间的至少一个第一电流脉冲，以及在随后的第二测试周期中具有第二未知持续时间的至少一个第二电流脉冲。 除了在正常操作状态下在互连上流动的第一电流之外，第二电流在第一测试周期期间在互连上流动，并且第三电流在测试操作状态期间在第二测试周期期间流动。
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公开(公告)号：US07313741B2
公开(公告)日：2007-12-25
申请号：US11145192
申请日：2005-06-06
IPC分类号： G01R31/28
CPC分类号： G11C29/1201 , G11C29/14 , G11C29/38
摘要： An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory has a combination circuit that generates the third data record on the output side from the data records fed to the combination circuit on the input side to ascertain based on the third data record whether the first and second data records have been fed to the combination circuit on the input side. The combination circuit generates the datum of the third data record with the first data value, if the first and second data records were fed to the combination circuit on the input side.
摘要翻译： 集成半导体存储器包括存储第一数据记录的存储器单元具有至少一个具有第一或第二数据值的数据，而第二数据记录具有至少一个具有第一或第二数据值的数据。 集成半导体存储器具有组合电路，其从在输入侧馈送到组合电路的数据记录在输出侧产生第三数据记录，以基于第三数据记录来确定第一和第二数据记录是否被馈送到 输入侧的组合电路。 如果第一和第二数据记录被馈送到输入侧的组合电路，则组合电路产生具有第一数据值的第三数据记录的数据。
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公开(公告)号：US07402859B2
公开(公告)日：2008-07-22
申请号：US11079884
申请日：2005-03-15
申请人： Joerg Vollrath , Marcin Gnat , Ralf Schneider , Stephan Schroeder
发明人： Joerg Vollrath , Marcin Gnat , Ralf Schneider , Stephan Schroeder
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L29/78696 , H01L27/10867 , H01L27/10873 , H01L29/0649 , H01L29/1037 , H01L29/42384 , H01L29/66757 , H01L29/66772 , H01L29/78606 , H01L29/78618
摘要： A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.
摘要翻译： 场效应半导体包括在半导体层的表面上彼此相邻布置的半导体层中具有表面的第一和第二半导体区域的半导体层，在第一半导体区域和第二半导体区域之间的绝缘层 半导体区域，半导体层的表面上的半导体条，该半导体条与第一半导体区域和第二半导体区域重叠，并与其邻接。 至少在绝缘层的区域中，栅极与半导体条重叠。 栅介质将栅极与半导体条绝缘在第一半导体区和第二半导体区之间。 半导体条和栅极形成为使得半导体条以第一预定栅极电压电绝缘并且在第二预定栅极电压下导电。
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公开(公告)号：US20050213269A1
公开(公告)日：2005-09-29
申请号：US11092885
申请日：2005-03-29
IPC分类号： G01R19/165 , G11C5/14 , G11C11/4074 , G11C29/00 , G11C29/48 , G11C29/50 , H02H3/00
CPC分类号： G11C5/143 , G01R19/16552 , G11C11/401 , G11C11/4074 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C2029/5004
摘要： An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.
摘要翻译： 集成电路包括具有用于施加参考电压的第一输入端子的电流发生器电路和用于施加由外部施加的电源电压内部由电压发生器电路产生的输入电压的第二输入端子。 电流发生器电路通过互连连接到输出端子。 在集成电路的测试操作状态下，第一电流在互连上流动。 电流发生器电路在随后的第二测试周期中在测试操作状态的第一测试周期和第二部分电流中产生第一部分电流。 部分电流各自叠加在互连上的第一电流上。 因此，在测试操作状态期间，输出端子发生三个电流。 电流发生器电路的内部产生的输入电压由三个电流和参考电压确定。
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公开(公告)号：US20050218960A1
公开(公告)日：2005-10-06
申请号：US11092963
申请日：2005-03-30
CPC分类号： G11C29/1201 , G01R31/275 , G01R31/2884 , G11C29/48 , G11C29/50 , G11C2029/5002
摘要： An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.
摘要翻译： 集成电路包括电路部件，第一控制电路和可切换电阻网络。 输入电压被馈送到输入侧的电路部件。 由第一控制电路产生的控制信号被馈送到电路部件的控制端。 利用可切换电阻网络，第一电阻或第二电阻连接在电路部件的输出端和集成电路的输出端之间，以在电路部件的输入侧和输出端之间产生电压降。 集成电路使得可以以取决于控制信号的方式在电路部件的输出端产生电流以及在电路部件的输入侧和输出端子之间落下的电压。 集成电路的晶体管的特性曲线族由集成电路确定。
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10.发明申请IC Chip Package, Test Equipment and Interface for Performing a Functional Test of a Chip Contained Within Said Chip Package 审中-公开IC芯片封装，用于执行所述芯片封装内包含的芯片的功能测试的测试设备和接口公开(公告)号：US20080079455A1
公开(公告)日：2008-04-03
申请号：US11866677
申请日：2007-10-03
申请人： Joerg Vollrath , Marcin Gnat , Ralf Schneider
发明人： Joerg Vollrath , Marcin Gnat , Ralf Schneider
IPC分类号： G01R31/26
CPC分类号： G11C29/56 , G01R1/07 , G01R31/2889 , G01R31/318533 , G01R31/31905 , G11C29/48 , G11C2029/5602 , H01L2224/4824
摘要： An interface between a test access port of an integrated circuit chip and a test equipment, which is designed to perform a functional test of the chip, is provided. The interface includes electric pads on either sides of the chip and the test equipment. The pads are arranged to interact by means of capacitive coupling, when a test data signal is input to one of the pads. Preferably, both pads are connected with either a receiver or a driver depending on the direction of the data flow. The electric pads relating to the chip's side may be arranged within the wiring substrate of a chip package, particularly along edge portion of the substrate, which encompasses an inner portion of the substrate, in which a ball-grid-array can be formed.
摘要翻译： 提供集成电路芯片的测试访问端口和被设计用于执行芯片的功能测试的测试设备之间的接口。 接口包括芯片两侧的电焊盘和测试设备。 当测试数据信号被输入到其中一个焊盘时，焊盘被布置成通过电容耦合相互作用。 优选地，两个焊盘根据数据流的方向与接收器或驱动器连接。 与芯片侧相关的电焊盘可以布置在芯片封装的布线基板内，特别是沿着基板的边缘部分，其包围可以形成球栅阵列的基板的内部。
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