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1.发明授权Reading circuit for nonvolatile analog memories, in particular flash-eeprom memories, with direct and constant current threshold voltage reading 有权用于非易失性模拟存储器的读取电路，特别是闪存存储器，具有直流和恒定电流阈值电压读数
公开(公告)号：US6034888A
公开(公告)日：2000-03-07
申请号：US239027
申请日：1999-01-27
申请人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Cedric Issartel , Pier Luigi Rolandi
发明人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Cedric Issartel , Pier Luigi Rolandi
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5642 , G11C27/005
摘要： The reading circuit comprises a current source, which, via a current reflection circuit, supplies a constant predetermined current to a cell to be read, an operational amplifier with a non-inverting input connected to the drain terminal of the cell, and an output connected to the gate terminal of the cell. The source terminal of the cell is connected to ground. Thereby the output voltage of the operational amplifier supplies directly (at the set current) the threshold voltage of the cell, and the drain terminal of the cell is biased to a positive voltage.
摘要翻译： 读取电路包括电流源，其经由电流反射电路向待读取的单元提供恒定的预定电流，具有连接到单元的漏极端子的非反相输入的运算放大器，以及连接的输出 到单元的门极。 电池的源极端子接地。 由此，运算放大器的输出电压直接（以设定电流）供给单元的阈值电压，并且单元的漏极端子偏置为正电压。
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2.发明授权Circuit for parallel programming nonvolatile memory cells, with adjustable programming speed 有权并行编程电路非易失性存储单元，具有可编程速度
公开(公告)号：US6163483A
公开(公告)日：2000-12-19
申请号：US447531
申请日：1999-11-23
CPC分类号： G11C16/12
摘要： A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.
摘要翻译： 一种具有电流镜电路的电路，具有第一节点和第二节点，分别连接到可控电流源和连接到所选存储器单元的漏极端子的公共节点。 第一运算放大器具有连接到第一节点和第二节点的输入，以及连接到所选择的存储器单元的控制端子并形成电路输出的输出。 第二运算放大器具有连接到斜坡发生器的第一输入端，连接到电路输出端的第二输入端，以及连接到可控电流源的控制输入端的输出端。 因此，两个负反馈环路将所选择的存储单元的漏极端子保持在足以编程的电压值，并且以导致所选择的存储单元写入的斜坡电压馈送存储单元的控制端子。 在第二节点和公共节点之间存在偏置源，使得在读取期间也可以使用相同的电路。
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3.发明授权Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices 有权用于控制擦除存储器件的方法，特别是模拟和多级闪存EEPROM器件
公开(公告)号：US6091642A
公开(公告)日：2000-07-18
申请号：US234942
申请日：1999-01-21
申请人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Frank Lhermet , Pierluigi Rolandi
发明人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Frank Lhermet , Pierluigi Rolandi
IPC分类号： G11C16/02 , G11C11/56 , G11C16/16 , G11C16/34 , G11C27/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C16/3409 , G11C11/56 , G11C11/5621 , G11C11/5635 , G11C16/16 , G11C16/3404 , G11C16/3445 , G11C27/005
摘要： The controlled erase method includes supplying at least one erase pulse to cells of a memory array; comparing the threshold voltage of the erased cells with a low threshold value; selectively soft-programming the erased cells which have a threshold voltage lower than the low threshold value; and verifying whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.
摘要翻译： 受控擦除方法包括向存储器阵列的单元提供至少一个擦除脉冲; 将擦除的单元的阈值电压与低阈值进行比较; 选择性地软编程具有低于低阈值的阈值电压的已擦除单元; 以及验证被擦除的单元是否具有低于低阈值的阈值电压。 如果至少一个预定数量的擦除单元具有高于高阈值的阈值电压，则将擦除脉冲施加到所有单元，并且重复比较选择性软编程和验证的步骤。
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4.发明授权Device and method for programming nonvolatile memory cells with automatic generation of programming voltage 有权用于自动生成编程电压来编程非易失性存储单元的装置和方法公开(公告)号：US06466481B1
公开(公告)日：2002-10-15
申请号：US09438232
申请日：1999-11-12
IPC分类号： G11C1606
CPC分类号： G11C16/12
摘要： The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped. The presence of a bias transistor between the second node and the memory cell enables use of the same circuit also during reading.
摘要翻译： 该器件包括电流镜电路，其具有分别连接到待编程的存储器单元的恒定电流源和漏极端子的第一和第二节点。 电压产生电路连接到第一节点以将其以恒定的参考电压（VR）偏置; 运算放大器具有连接到第一节点的反相输入端，连接到第二节点的非反相输入端，以及连接到存储器单元的控制端子的输出端。 因此，存储单元的漏极端子被偏置在具有足以编程的值的恒定参考电压，并且运算放大器和存储单元形成负反馈回路，其在存储单元的控制端上提供 导致存储单元写入的斜坡电压（VPCX）。 斜坡电压以与阈值电压相同的速度增加，因此可以用于知道什么时候达到期望的阈值，并且因此当必须停止编程时。 在第二节点和存储器单元之间存在偏置晶体管，在读取期间也可以使用相同的电路。
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5.发明授权Circuit for high-precision analog reading of nonvolatile memory cells, in particular analog or multilevel flash or EEPROM memory cells 有权用于高精度模拟读取非易失性存储单元的电路，特别是模拟或多电平闪存或EEPROM存储单元
公开(公告)号：US6128228A
公开(公告)日：2000-10-03
申请号：US438823
申请日：1999-11-12
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5642 , G11C27/005
摘要： An analog read circuit includes an output transistor connected to a memory cell to be read, and an operational amplifier having a non-inverting input connected to the drain terminal of the memory cell, an inverting input connected to a reference terminal, and an output, forming the output of the reading circuit and connected to the gate terminal of the output transistor. Bias transistors maintain the memory cell and the output transistor in the linear region, and the operational amplifier and the output transistor form a negative feedback loop so that the output voltage V.sub.O of the read circuit is linerly dependent upon the threshold voltage the memory cell. The reading circuit has high precision and high reading speed.
摘要翻译： 模拟读取电路包括连接到要读取的存储单元的输出晶体管，和具有连接到存储单元的漏极端子的非反相输入的运算放大器，连接到参考端子的反相输入端和输出端， 形成读出电路的输出并连接到输出晶体管的栅极端。 偏置晶体管将存储单元和输出晶体管保持在线性区域中，并且运算放大器和输出晶体管形成负反馈回路，使得读取电路的输出电压VO在线性地取决于存储器单元的阈值电压。 读取电路精度高，读取速度快。
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6.发明授权Voltage regulator for driving plural loads based on the number of loads being driven 有权电压调节器，用于根据被驱动的负载数来驱动多个负载公开(公告)号：US06232753B1
公开(公告)日：2001-05-15
申请号：US09467726
申请日：1999-12-20
IPC分类号： G05F1557
CPC分类号： G05F1/565
摘要： A voltage regulator is provided for limiting overcurrents when used with a plurality of loads, particularly in flash memories, which are connected between an output node of the regulator and a voltage reference by way of a plurality of switches. The voltage regulator includes at least one differential stage that has a non-inverting input terminal for a control voltage, and an inverting input terminal connected to the voltage reference and the output node of the regulator through a feedback network. There is an output terminal connected to the output node of the voltage regulator to produce an output reference voltage from a comparison of input voltages. In the voltage regulator is a main control transistor connected between a high-voltage reference and the output terminal of the regulator. Advantageously, the regulator further includes a number of balance transistors connected between the high-voltage reference and the output node of the regulator and driven according to the load being connected to the output node, thereby to shorten the duration of an overcurrent at the output terminal while delivering the current required by the loads.
摘要翻译： 提供了一种电压调节器，用于在多个负载（特别是闪存）中使用时，限制过电流，其通过多个开关连接在调节器的输出节点和电压基准之间。 电压调节器包括至少一个差分级，其具有用于控制电压的非反相输入端，反相输入端通过反馈网连接到稳压器的电压基准和输出节点。 输出端连接到电压调节器的输出节点，以从输入电压的比较产生输出参考电压。 在电压调节器中是连接在高压基准和调节器的输出端之间的主控晶体管。 有利地，调节器还包括连接在调节器的高压基准和输出节点之间的多个平衡晶体管，其根据连接到输出节点的负载而驱动，从而缩短输出端子处的过电流的持续时间 同时提供负载所需的电流。
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7.发明授权Device for reading analog nonvolatile memory cells, in particular flash cells 有权读取模拟非易失性存储单元，特别是闪存单元的设备公开(公告)号：US06195289B1
公开(公告)日：2001-02-27
申请号：US09425446
申请日：1999-10-22
IPC分类号： G11C1606
CPC分类号： G11C16/26 , G11C11/5621 , G11C11/5642 , G11C27/005 , G11C27/02
摘要： A read device comprises a sense amplifier having an input connected to a data memory cell to be read and an output issuing a signal correlated to the threshold voltage of the data memory cell. A first and second voltage sources circuit have respect first and second outputs that supply respective first and a second input reference voltage. A resistive divider connected between the first and the second outputs of the voltage source circuits has a plurality of outputs supplying respective intermediate reference voltages having values between the first and the second input reference voltages. A plurality of comparator circuits have a first input connected to the output of the sense amplifier, a second input connected to a respective output of the resistive divider, and an output supplying a digital signal indicative of the outcome of a respective comparison. Each voltage source circuit comprises a nonvolatile reference memory cell of the same type as the data memory cell and having an own threshold voltage correlated to the input reference voltage, supplied by the voltage source circuit. Thereby, the input reference voltages, and thus the intermediate reference voltages supplied to the comparator circuits, undergo variations in time correlated to the voltage supplied by the sense amplifier and consequent on the variations of the threshold voltages of the data memory cells.
摘要翻译： 读取装置包括具有连接到要读取的数据存储单元的输入的读出放大器和发出与数据存储单元的阈值电压相关的信号的输出。 第一和第二电压源电路涉及提供相应的第一和第二输入参考电压的第一和第二输出。 连接在电压源电路的第一和第二输出之间的电阻分压器具有多个输出，其提供具有在第一和第二输入参考电压之间的值的各个中间参考电压。 多个比较器电路具有连接到读出放大器的输出端的第一输入端，连接到电阻分压器的相应输出端的第二输入端，以及提供指示相应比较结果的数字信号的输出端。 每个电压源电路包括与数据存储单元相同类型的非易失性参考存储单元，并具有由电压源电路提供的与输入参考电压相关的自身阈值电压。 因此，输入参考电压以及因此提供给比较器电路的中间参考电压经历与由读出放大器提供的电压相关的时间变化，并且由此导致数据存储单元的阈值电压的变化。
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8.发明授权Method for high precision programming nonvolatile memory cells, with optimized programming speed 有权高精度编程非易失性存储单元的方法，具有优化的编程速度公开(公告)号：US06392931B1
公开(公告)日：2002-05-21
申请号：US09449168
申请日：1999-11-24
IPC分类号： G11C700
CPC分类号： G11C16/3486 , G11C11/5628 , G11C16/12 , G11C27/005
摘要： A programming method comprises the steps of applying a ramp voltage having a first slope to the gate terminal of a selected memory cell to rapidly bring the threshold voltage of the selected cell to an intermediate value; then applying a ramp voltage having a second slope lower than the first, to end programming to the desired final threshold value with high precision. Thereby, when a high threshold value is to be programmed, programming time is reduced; on the other hand, if a low threshold value is to be programmed, the slower ramp voltage is applied right from the start, to prevent possible overprogramming of the cell.
摘要翻译： 一种编程方法包括以下步骤：向所选择的存储单元的栅极端施加具有第一斜率的斜坡电压，以将所选择的单元的阈值电压快速地转换成中间值; 然后施加具有低于第一斜率的第二斜率的斜坡电压，以高精度将编程结束到期望的最终阈值。 因此，当要编程高阈值时，编程时间减少; 另一方面，如果要编程低阈值，则从开始直接施加较慢的斜坡电压，以防止单元可能的过度编程。
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9.发明授权Device for reading non-volatile memory cells in particular analog flash memory cells 失效用于读取特定模拟闪存单元中的非易失性存储单元的装置公开(公告)号：US06323799B1
公开(公告)日：2001-11-27
申请号：US09421616
申请日：1999-10-19
IPC分类号： H03M112
CPC分类号： G11C16/34 , G11C7/16 , G11C11/5621 , G11C11/5642 , G11C16/26 , G11C27/005 , G11C2211/5642
摘要： A reading device having an A/D converter of n+m bits receiving an input signal correlated to the threshold voltage of the memory cell, and supplying a binary output word of n+m bits. The A/D converter is of a double conversion stage type, wherein a first A/D conversion stage carries out a first analog/digital conversion of the input signal to supply at the output a first intermediate binary word of n bits, and the second A/D conversion stage can be activated selectively to carry out a second analog/digital conversion of a difference signal correlated to the difference between the input signal and the value of the first intermediate binary word. The second A/D conversion stage generates at the output a second intermediate binary word of m bits that is supplied along with the first intermediate binary word to an adder, which generates the binary output word of n+m bits.
摘要翻译： 一种读取装置，具有n + m位的A / D转换器，接收与存储单元的阈值电压相关的输入信号，并提供n + m位的二进制输出字。 A / D转换器是双转换级类型，其中第一A / D转换级执行输入信号的第一模/数转换，以在输出端提供n位的第一中间二进制字，第二 可以选择性地激活A / D转换级，以对与输入信号和第一中间二进制字的值之间的差相关的差分信号进行第二模拟/数字转换。 第二A / D转换级在输出端产生与第一中间二进制字一起提供的m位的第二中间二进制字到加法器，该加法器产生n + m位的二进制输出字。
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公开(公告)号：US06687167B2
公开(公告)日：2004-02-03
申请号：US10225513
申请日：2002-08-20
申请人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
发明人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
IPC分类号： G11C1604
摘要： A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
摘要翻译： 一种非易失性半导体存储器件，包括连接到行线和两个电源端子的输出。 每个基本级具有具有p沟道MOS晶体管的上部分支和具有n沟道MOS晶体管的下部分支。 为了允许逐行擦除存储器，而不必使用能够承受高电压的部件，每个基本级具有两个辅助MOS晶体管，即上部支路中的n沟道晶体管和 下分支。 以这种方式，可以以这种方式偏置基本级，在读取和编程阶段，上部分支将用作上拉和下部分支作为下拉，而在擦除阶段，上部分支作为 下拉和下部分支作为上拉。
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