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1.发明授权Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices 有权用于控制擦除存储器件的方法，特别是模拟和多级闪存EEPROM器件
公开(公告)号：US6091642A
公开(公告)日：2000-07-18
申请号：US234942
申请日：1999-01-21
申请人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Frank Lhermet , Pierluigi Rolandi
发明人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Frank Lhermet , Pierluigi Rolandi
IPC分类号： G11C16/02 , G11C11/56 , G11C16/16 , G11C16/34 , G11C27/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C16/3409 , G11C11/56 , G11C11/5621 , G11C11/5635 , G11C16/16 , G11C16/3404 , G11C16/3445 , G11C27/005
摘要： The controlled erase method includes supplying at least one erase pulse to cells of a memory array; comparing the threshold voltage of the erased cells with a low threshold value; selectively soft-programming the erased cells which have a threshold voltage lower than the low threshold value; and verifying whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.
摘要翻译： 受控擦除方法包括向存储器阵列的单元提供至少一个擦除脉冲; 将擦除的单元的阈值电压与低阈值进行比较; 选择性地软编程具有低于低阈值的阈值电压的已擦除单元; 以及验证被擦除的单元是否具有低于低阈值的阈值电压。 如果至少一个预定数量的擦除单元具有高于高阈值的阈值电压，则将擦除脉冲施加到所有单元，并且重复比较选择性软编程和验证的步骤。
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2.发明授权Reading circuit for nonvolatile analog memories, in particular flash-eeprom memories, with direct and constant current threshold voltage reading 有权用于非易失性模拟存储器的读取电路，特别是闪存存储器，具有直流和恒定电流阈值电压读数
公开(公告)号：US6034888A
公开(公告)日：2000-03-07
申请号：US239027
申请日：1999-01-27
申请人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Cedric Issartel , Pier Luigi Rolandi
发明人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Cedric Issartel , Pier Luigi Rolandi
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5642 , G11C27/005
摘要： The reading circuit comprises a current source, which, via a current reflection circuit, supplies a constant predetermined current to a cell to be read, an operational amplifier with a non-inverting input connected to the drain terminal of the cell, and an output connected to the gate terminal of the cell. The source terminal of the cell is connected to ground. Thereby the output voltage of the operational amplifier supplies directly (at the set current) the threshold voltage of the cell, and the drain terminal of the cell is biased to a positive voltage.
摘要翻译： 读取电路包括电流源，其经由电流反射电路向待读取的单元提供恒定的预定电流，具有连接到单元的漏极端子的非反相输入的运算放大器，以及连接的输出 到单元的门极。 电池的源极端子接地。 由此，运算放大器的输出电压直接（以设定电流）供给单元的阈值电压，并且单元的漏极端子偏置为正电压。
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3.发明授权Method for multilevel programming of a nonvolatile memory, and a multilevel nonvolatile memory 有权用于非易失性存储器和多级非易失性存储器的多级编程的方法
公开(公告)号：US06011715A
公开(公告)日：2000-01-04
申请号：US185906
申请日：1998-11-03
CPC分类号： G11C11/5621 , G11C11/5628
摘要： A programming method for a nonvolatile memory includes the steps of: a) determining a current value of the threshold voltage; b) acquiring a target value of the threshold voltage; c) calculating a first number of gate voltage pulses necessary to take the threshold voltage from the current value to the target value; d) applying a second number of consecutive voltage pulses to the gate terminal of the cell, the second number being correlated to the first number and having a uniformly increasing amplitude; e) then measuring a current value of the threshold voltage; and repeating steps c) to e) until a final threshold value is obtained.
摘要翻译： 一种用于非易失性存储器的编程方法包括以下步骤：a）确定阈值电压的当前值; b）获取阈值电压的目标值; c）计算将阈值电压从当前值到目标值所需的第一数量的栅极电压脉冲; d）将第二数量的连续电压脉冲施加到所述单元的栅极端子，所述第二数量与所述第一数量相关并具有均匀增加的幅度; e）然后测量阈值电压的当前值; 并重复步骤c）至e），直到获得最终阈值。
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4.发明授权公开(公告)号：US06195283B1
公开(公告)日：2001-02-27
申请号：US09076013
申请日：1998-05-11
IPC分类号： G11C700
CPC分类号： G11C27/005
摘要： For each memory cell to be programmed, the present threshold value of the cell is determined; the desired threshold value is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells of a memory array which is connected to a single word line and to different bit lines, each with a programming pulse the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.
摘要翻译： 对于要编程的每个存储器单元，确定单元的当前阈值; 获取期望的阈值; 计算当前阈值与期望阈值之间的模拟距离; 然后产生编程脉冲，其持续时间与计算出的模拟距离成比例。 重复编程和读取周期，直到达到所需的阈值。 由于中间读取步骤数量的减少，可以节省时间。 该方法允许并行地编程存储器阵列的多个单元，其连接到单个字线和不同的位线，每个存储器阵列的编程脉冲的持续时间与为同一个字线计算的模拟距离成比例 细胞。 编程过程非常快，因为编程的并行应用和中间阅读周期的节省。
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5.发明授权Method and device for analog programming of flash EEPROM memory cells with autoverify 有权用于自动验证的闪存EEPROM存储单元的模拟编程方法和设备
公开(公告)号：US6081448A
公开(公告)日：2000-06-27
申请号：US162639
申请日：1998-09-28
CPC分类号： G11C27/005
摘要： A device for analog programming is disclosed. The device comprises a current mirror circuit connected to drain terminals of a cell to be programmed and of a MOS reference transistor. An operational amplifier has inputs connected to the drain terminals of the cell and respectively of the MOS transistor and an output connected to the control terminal of the MOS transistor. During programming, the control and drain terminals of the cell are biased at corresponding programming voltages and the output voltage of the operational amplifier, which is correlated to the current threshold voltage level of the cell, is monitored and the programming is interrupted when this output voltage becomes at least equal to a reference voltage correlated to the threshold value desired for the cell.
摘要翻译： 公开了一种用于模拟编程的装置。 该器件包括连接到要编程的单元的漏极端子和MOS参考晶体管的电流镜电路。 运算放大器具有连接到单元的漏极端子和MOS晶体管的漏极端子和连接到MOS晶体管的控制端子的输出的输入。 在编程期间，单元的控制和漏极端子以相应的编程电压被偏置，并且监视与电池的当前阈值电压电平相关的运算放大器的输出电压，并且当该输出电压 变得至少等于与小区所需的阈值相关的参考电压。
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6.发明授权Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMS 有权用于非易失性存储器件，特别是闪速存储器和EEPROMS的并行编程的方法
公开(公告)号：US6069822A
公开(公告)日：2000-05-30
申请号：US181230
申请日：1998-10-27
CPC分类号： G11C16/3459 , G11C16/3454
摘要： The programming method comprises the steps of applying a programming pulse to a first cell and simultaneously verifying the present threshold value of at least a second cell; then verifying the present threshold value of the first cell and simultaneously applying a programming pulse to the second cell. In practice, during the entire programming operation, the gate terminal of both the cells is biased to a same predetermined gate voltage and the source terminal is connected to ground; the step of applying a programming pulse is carried out by biasing the drain terminal of the cell to a predetermined programming voltage and the step of verifying is carried out by biasing the drain terminal of the cell to a read voltage different from the programming voltage. Thereby, switching between the step of applying a programming pulse and verifying is obtained simply by switching the drain voltage of the cells.
摘要翻译： 编程方法包括以下步骤：将编程脉冲施加到第一单元并且同时验证至少第二单元的当前阈值; 然后验证第一小区的当前阈值并同时向第二小区施加编程脉冲。 实际上，在整个编程操作期间，两个单元的栅极端子被偏置到相同的预定栅极电压，并且源极端子接地; 通过将单元的漏极端子偏置到预定的编程电压来执行编程脉冲的步骤，并且通过将单元的漏极端子偏压到与编程电压不同的读取电压来执行验证步骤。 因此，简单地通过切换单元的漏极电压来获得施加编程脉冲和验证的步骤之间的切换。
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7.发明授权High-precision analog reading circuit for flash analog memory arrays using negative feedback 失效用于闪存模拟存储器阵列的高精度模拟读取电路使用负反馈
公开(公告)号：US6016272A
公开(公告)日：2000-01-18
申请号：US60165
申请日：1998-04-14
CPC分类号： G11C16/28 , G11C27/005
摘要： An analog reading circuit having a current mirror circuit forcing two identical currents into a cell to be read and into a reference cell. An operational amplifier has an inverting input connected to the drain terminal of the cell to be read, a non-inverting input connected to the drain terminal of the reference cell, and an output connected to the gate terminal of the reference cell. The reference cell therefore forms part of a negative feedback loop which maintains the overdrive voltages of the cell to be read and the reference cell constant, irrespective of temperature variations. The reading circuit is also of high precision and has a high reading speed.
摘要翻译： 一种具有电流镜像电路的模拟读取电路，其将两个相同的电流强制进入待读取的单元并进入参考单元。 运算放大器具有连接到要读取的单元的漏极端子的反相输入端，连接到参考单元的漏极端子的非反相输入端和连接到参考单元栅极端子的输出端。 因此，参考单元形成负反馈回路的一部分，其保持要读取的单元的过驱动电压和参考单元恒定，而与温度变化无关。 读取电路也具有高精度，读取速度快。
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8.发明授权Circuit and method of reading cells of an analog memory array, in particular of the flash type 失效读取模拟存储器阵列的单元的电路和方法，特别是闪存类型
公开(公告)号：US5973959A
公开(公告)日：1999-10-26
申请号：US121024
申请日：1998-07-22
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/26 , G11C2211/5645 , G11C27/02
摘要： A reading circuit comprises a current mirror circuit connected, at a first and a second output node, to the drain terminals of an array cell and of a reference cell; a comparator whose inputs are connected to the output nodes of the current mirror circuit; a ramp generator having an enabling input connected to the output of the comparator and an output connected to the control terminal of the reference cell. Biasing the gate terminal of the array cell to a constant voltage, when the currents flowing in the array cell and in the reference cell are equal, the value assumed by the ramp voltage is proportional to the threshold value of the array cell; at that time the comparator is triggered and discontinues the ramp increase, supplying as output the desired threshold value.
摘要翻译： 读取电路包括在第一和第二输出节点处连接到阵列单元和参考单元的漏极端子的电流镜电路; 比较器，其输入端连接到电流镜电路的输出节点; 斜坡发生器，其具有连接到比较器的输出的使能输入和连接到参考单元的控制端的输出。 当阵列单元和参考单元中流动的电流相等时，将阵列单元的栅极端子偏置为恒定电压，斜坡电压所假定的值与阵列单元的阈值成比例; 此时比较器被触发并停止斜坡增加，作为输出提供所需的阈值。
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公开(公告)号：US5978025A
公开(公告)日：1999-11-02
申请号：US754589
申请日：1996-11-20
CPC分类号： H04N5/353 , H04N5/374 , H04N5/3765 , H04N5/378
摘要： An integrated image processing system includes an array of cells arranged in rows and columns. Each cell corresponds to a pixel of an image and includes a photosensitive element for detecting the luminous intensity of its respective pixel and for generating a value. A first switch controls the transfer of the value from a respective photosensitive element to the corresponding capacitor, which stores the value. A second switch couples each of the cells in parallel to a common line. A control circuit receives the values from each cell on the common line and generates a signal for regulating the switching time interval of the first switch.
摘要翻译： 集成图像处理系统包括以行和列排列的单元阵列。 每个单元对应于图像的像素，并且包括用于检测其各个像素的发光强度并用于产生值的光敏元件。 第一开关控制从相应的感光元件转移到存储该值的对应的电容器。 第二开关将每个单元并联连接到公共线。 控制电路接收公共线上的每个单元的值，并产生用于调节第一开关的切换时间间隔的信号。
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10.发明授权Current comparator with intrinsic limitation of absorption to the lowest current level 失效电流比较器具有吸收到最低电流水平的固有限制
公开(公告)号：US5770954A
公开(公告)日：1998-06-23
申请号：US728396
申请日：1996-10-09
CPC分类号： H03F3/345 , G05F3/262 , H03K5/2472
摘要： A method and a respective circuit arrangement capable of markedly limiting the absorption of current by a current comparator circuit. The invention consists in limiting the absorption of current through the branch of the comparator circuit, along which is forced the highest current to the value of the lowest current, which is in turn forced through the other branch of the comparator circuit. This condition is obtained without interfering in any way with other characteristics of switching speed and sensitivity of the comparator circuit.
摘要翻译： 一种能够显着限制电流比较器电路对电流的吸收的方法和各自的电路装置。 本发明限制了通过比较器电路的分支的电流的吸收，沿着该比较电路迫使最大电流达到最低电流的值，该电流又被迫通过比较器电路的另一个分支。 获得该条件而不以任何方式干扰比较器电路的开关速度和灵敏度的其他特性。
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