公开(公告)号：US5506161A

公开(公告)日：1996-04-09

申请号：US328317

申请日：1994-10-24

申请人： Marius Orlowski ,  Shih K. Cheng

发明人： Marius Orlowski ,  Shih K. Cheng

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66492 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7836

摘要： Insulated gate semiconductor device (10) and a method of manufacturing the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) includes an N-channel transistor (55) and a P-channel transistor (60). The N-channel transistor (55) has a gate electrode (22') that has a central portion (22) and gate electrode extensions (41) adjacent to the central portion (22). Likewise the P-channel transistor (60) has a gate electrode (24') that has a central portion (24) and gate electrode extensions (42) adjacent to the central portion (24). The gate electrode extensions (41, 42) are formed by filling openings (34, 36) with a gate electrode material. The openings are used for the formation of graded channel regions underneath the gate electrode extensions (41, 42).

摘要翻译： 绝缘栅半导体器件（10）和绝缘栅半导体器件（10）的制造方法。 绝缘栅半导体器件（10）包括N沟道晶体管（55）和P沟道晶体管（60）。 N沟道晶体管（55）具有栅电极（22'），其具有与中心部分（22）相邻的中心部分（22）和栅电极延伸部分（41）。 类似地，P沟道晶体管（60）具有栅电极（24'），其具有与中心部分（24）相邻的中心部分（24）和栅电极延伸部分（42）。 通过用栅电极材料填充开口（34,36）形成栅电极延伸部（41,42）。 这些开口用于在栅电极延伸部（41,42）下形成渐变沟道区。

公开(公告)号：US5545575A

公开(公告)日：1996-08-13

申请号：US328312

申请日：1994-10-24

申请人： Shih K. Cheng ,  Marius Orlowski

发明人： Shih K. Cheng ,  Marius Orlowski

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/265

CPC分类号： H01L29/66583 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/66659

摘要： Insulated gate semiconductor device (10) and a method of manufacturing the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) includes an N-channel transistor (15) and a P-channel transistor (16). The N-channel transistor (15) has a gate electrode (35) that has a central portion (28) and two adjacent gate extensions (49, 52). Likewise the P-channel transistor (16) has a gate electrode (35') which has a central portion (29) and two adjacent gate extensions (53, 54). The gate extensions (49, 52, 53, 54) allow the formation of graded channel regions underneath the gate electrodes (35, 35') and adjacent to the source (57, 59) and drain (58, 62) regions by offsetting an LDD or a single heavily doped source/drain implant from channel regions which are covered by the gate extensions (49, 52 53, 54).

摘要翻译： 绝缘栅半导体器件（10）和绝缘栅半导体器件（10）的制造方法。 绝缘栅半导体器件（10）包括N沟道晶体管（15）和P沟道晶体管（16）。 N沟道晶体管（15）具有栅电极（35），其具有中心部分（28）和两个相邻的栅极延伸部分（49,52）。 类似地，P沟道晶体管（16）具有栅电极（35'），其具有中心部分（29）和两个相邻的栅极延伸部（53,54）。 栅极延伸部分（49,52,53,54）允许在栅极电极（35,35'）下方并且邻近源极（57,59）和漏极（58,62）区域之间形成渐变沟道区域， LDD或来自由栅极延伸部分（49,52,53,54）覆盖的沟道区域的单个重掺杂源极/漏极注入。

公开(公告)号：US20170155045A1

公开(公告)日：2017-06-01

申请号：US15365445

申请日：2016-11-30

申请人： Marius Orlowski ,  Gargi Ghosh ,  Anshuman Verma

发明人： Marius Orlowski ,  Gargi Ghosh ,  Anshuman Verma

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/149 ,  G11C11/5614 ,  G11C13/0011 ,  G11C2013/0078 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146

摘要： A memory device having a first array of first electrodes extending along a first direction made from a first material and a second array of second electrodes extending along a second direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell, said memory cell formed by a conductive path between said first and second electrodes.

公开(公告)号：US08552501B2

公开(公告)日：2013-10-08

申请号：US13447369

申请日：2012-04-16

申请人： Marius Orlowski ,  Andreas Wild

发明人： Marius Orlowski ,  Andreas Wild

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7854 ,  H01L29/66795 ,  H01L29/78687

摘要： A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.

摘要翻译： 形成具有用于反向T沟道场效应晶体管ITFET器件的垂直沟道部分和水平沟道部分的反向T形沟道结构的方法包括半导体衬底，半导体衬底上的第一半导体材料的第一层和第二层 在第一层上的第二半导体材料。 选择第一和第二半导体材料，使得第一半导体材料具有小于除去第二半导体材料的速率的去除速率。

公开(公告)号：US08202798B2

公开(公告)日：2012-06-19

申请号：US12675242

申请日：2007-09-20

申请人： Greg Braeckelmann ,  Hisao Kawasaki ,  Marius Orlowski ,  Emmanuel Petitprez

发明人： Greg Braeckelmann ,  Hisao Kawasaki ,  Marius Orlowski ,  Emmanuel Petitprez

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterized in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.

摘要翻译： 一种包括一个或多个电介质层的集成电路，其中或每个电介质层设置有一个或多个互连，其中互连包括当电流流动时从互连的第一区域移动到互连的第二区域的金属原子，其特征在于 互连件包括在互连的第一区域中的供体区域，用于提供金属原子，以便补偿来自第一区域的原子的移动以及用于接收金属原子的互连的第二区域处的受体区域，以便补偿运动 的原子到第二个区域。

公开(公告)号：US20100044762A1

公开(公告)日：2010-02-25

申请号：US12605556

申请日：2009-10-26

申请人： Marius Orlowski

发明人： Marius Orlowski

IPC分类号： H01L29/78 ,  H01L29/772

CPC分类号： H01L29/78684 ,  H01L29/66818 ,  H01L29/785

摘要： A non-planar semiconductor device (10) starts with a silicon fin (42). A source of germanium (e.g. 24, 26, 28, 30, 32) is provided to the fin (42). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation (30) to provide germanium; other methods may also be used to provide germanium. The fin (42) is then oxidized to form a silicon germanium channel region in the fin (36). In some embodiments, the entire fin (42) is transformed from silicon to silicon germanium. One or more fins (36) may be used to form a non-planar semiconductor device, such as, for example, a FINFET, MIGFET, Tri-gate transistor, or multi-gate transistor.

摘要翻译： 非平面半导体器件（10）从硅片（42）开始。 将锗源（例如24,26,28,30,32）提供给翅片（42）。 一些实施例可以使用沉积来提供锗; 一些实施例可以使用离子注入（30）来提供锗; 也可以使用其它方法来提供锗。 然后将翅片（42）氧化以在翅片（36）中形成硅锗通道区域。 在一些实施例中，整个鳍（42）从硅转变为硅锗。 可以使用一个或多个翅片（36）来形成非平面半导体器件，例如FINFET，MIGFET，三栅极晶体管或多栅极晶体管。

公开(公告)号：US20080006880A1

公开(公告)日：2008-01-10

申请号：US11857122

申请日：2007-09-18

申请人： Marius Orlowski ,  Suresh Venkatesan

发明人： Marius Orlowski ,  Suresh Venkatesan

IPC分类号： H01L29/76

CPC分类号： H01L29/7846 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78687

摘要： A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axially stress are both compressive for P-channel transistors and tensile for N-channel transistors. Both transistor types can be included on the same integrated circuit.

摘要翻译： 提出了一种在晶体管的沟道区域中提供迁移率增强的方法和装置。 在一个实施例中，沟槽区域（18）形成在双轴向应力的衬底上。 源极（30）和漏极（32）区域形成在衬底上。 源极和漏极区域向双向应力通道区域提供额外的单轴应力。 单向应力和双轴向应力对于P沟道晶体管是压缩的，对于N沟道晶体管是拉伸的。 两种晶体管类型都可以包含在同一集成电路中。

公开(公告)号：US20070235807A1

公开(公告)日：2007-10-11

申请号：US11742955

申请日：2007-05-01

申请人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

发明人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66772

摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

摘要翻译： 在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。 衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。 底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。 然后在氧掺杂半导体层上外延生长半导体层。 在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。 然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。 不同类型的晶体管形成在不同的结晶取向上。

公开(公告)号：US20070218628A1

公开(公告)日：2007-09-20

申请号：US11375890

申请日：2006-03-15

申请人： Marius Orlowski ,  Suresh Venkatesan

发明人： Marius Orlowski ,  Suresh Venkatesan

IPC分类号： H01L21/8242

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66795 ,  H01L29/785

摘要： An electronic device can include a base layer, a semiconductor layer, and a first semiconductor fin spaced apart from and overlying a semiconductor layer. In a particular embodiment, a second semiconductor fin can include a portion of the semiconductor layer. In another aspect, a process of forming an electronic device can include providing a workpiece that includes a base layer, a first semiconductor layer that overlies and is spaced apart from a base layer, a second semiconductor layer that overlies, and an insulating layer lying between the first semiconductor layer and the second semiconductor layer. The process can also include removing a portion of the second semiconductor layer to form a first semiconductor fin, and forming a conductive member overlying the first semiconductor fin.

摘要翻译： 电子器件可以包括基极层，半导体层和与半导体层间隔开并覆盖半导体层的第一半导体鳍片。 在特定实施例中，第二半导体鳍片可以包括半导体层的一部分。 另一方面，形成电子器件的工艺可以包括提供一种工件，其包括基底层，覆盖并与基底层间隔开的第一半导体层，覆盖在第二半导体层上的绝缘层和位于第二半导体层之间的绝缘层 第一半导体层和第二半导体层。 该工艺还可以包括去除第二半导体层的一部分以形成第一半导体鳍片，以及形成覆盖在第一半导体鳍片上的导电构件。

公开(公告)号：US20070176247A1

公开(公告)日：2007-08-02

申请号：US11343623

申请日：2006-01-30

申请人： Chun-Li Liu ,  Marius Orlowski ,  Matthew Stoker

发明人： Chun-Li Liu ,  Marius Orlowski ,  Matthew Stoker

IPC分类号： H01L29/94

CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.

摘要翻译： 为半导体器件提供了方法和装置。 该装置包括其中具有源极区和漏极区的衬底，漏极区被延伸到衬底的第一表面的沟道区分离，以及位于沟道区上方的多层栅极结构。 栅极结构包括：栅极电介质，优选地与沟道区基本上接触的Hf，Zr或HfZr的氧化物，例如覆盖栅极电介质的MoSi的氧化物的第一导体层， 例如多晶硅，覆盖在第一导体层上并且适于向沟道区施加电场，以及位于第一导体层上方或下方的杂质迁移抑制层（例如MoSi），并适于抑制移动 杂质，例如氧气，朝向衬底。