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    Magnetoresistive random access memory device and method of fabrication thereof
    5.
    发明授权
    Magnetoresistive random access memory device and method of fabrication thereof 失效
    磁阻随机存取存储器件及其制造方法

    公开(公告)号：US06518071B1

    公开(公告)日：2003-02-11

    申请号：US10109429

    申请日：2002-03-28

    申请人： Mark A. Durlam ,  Mark F. Deherrera ,  Kelly W. Kyler ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Steven M. Smith ,  Charles Snyder ,  Jon M. Slaughter

    发明人： Mark A. Durlam ,  Mark F. Deherrera ,  Kelly W. Kyler ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Steven M. Smith ,  Charles Snyder ,  Jon M. Slaughter

    IPC分类号： H01L2100

    CPC分类号： H01L43/12

    摘要： A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.

    摘要翻译： 一种制造具有锥形的MRAM器件的方法，包括以下步骤：提供衬底，形成位于衬底上的电介质区域，对介质区域进行图案化和各向同性地蚀刻到衬底以形成沟槽，将MRAM器件沉积在 沟槽，其中MRAM器件包括位于衬底上的宽度的第一铁磁区域，具有位于第一铁磁区域上的宽度的非铁磁间隔层，以及位于非铁磁间隔层上的宽度的第二铁磁区域 其中所述锥形通过使所述第一铁磁性区域的宽度大于所述非铁磁间隔层的宽度而形成，并且所述非铁磁隔离层的宽度大于所述第二铁磁区域的宽度，使得所述第一铁磁性区域 区域与第二铁磁区域分离。

    Magnetoelectronic devices utilizing protective capping layers and methods of fabricating the same
    7.
    发明授权
    Magnetoelectronic devices utilizing protective capping layers and methods of fabricating the same 有权
    使用保护盖层的磁电子器件及其制造方法

    公开(公告)号：US07087972B1

    公开(公告)日：2006-08-08

    申请号：US11048015

    申请日：2005-01-31

    申请人： J. Jack Ren ,  Brian R. Butcher ,  Mark A. Durlam ,  Gregory W. Grynkewich

    发明人： J. Jack Ren ,  Brian R. Butcher ,  Mark A. Durlam ,  Gregory W. Grynkewich

    IPC分类号： H01L29/82

    CPC分类号： H01L43/12 ,  H01L27/228

    摘要： Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.

    摘要翻译： 提供了磁电子器件结构及其制造方法。 一种方法包括形成第一和第二导体。 第一导体电耦合到互连叠层。 沉积在第一导体和第二导体上的第一绝缘层。 蚀刻通孔以基本上暴露第一导体。 通过无孔沉积在通孔内沉积保护性覆盖层并电耦合到第一导体。 磁通存储元件层形成在通孔内并覆盖第二绝缘层和第二导体。

    Methods and structures for electrical communication with an overlying electrode for a semiconductor element
    8.
    发明授权
    Methods and structures for electrical communication with an overlying electrode for a semiconductor element 有权
    用于与半导体元件的上覆电极电连通的方法和结构

    公开(公告)号：US07105903B2

    公开(公告)日：2006-09-12

    申请号：US10993196

    申请日：2004-11-18

    申请人： Brian R. Butcher ,  Gregory W. Grynkewich ,  Kelly W. Kyler ,  Kenneth H. Smith ,  Richard G. Williams

    发明人： Brian R. Butcher ,  Gregory W. Grynkewich ,  Kelly W. Kyler ,  Kenneth H. Smith ,  Richard G. Williams

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L29/82 ,  H01L43/00

    CPC分类号： H01L43/12 ,  H01L27/226

    摘要： Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the semiconductor element. The second electrode has a lateral dimension that is less than the lateral dimension of the first electrode. A conductive hardmask overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element is in electrical communication with the conductive hardmask.

    摘要翻译： 提供了用于与半导体元件的上覆电极的电连通的结构以及用于制造这种结构的方法。 与上覆电极电连通的结构包括具有横向尺寸的第一电极，覆盖第一电极的半导体元件和覆盖半导体元件的第二电极。 第二电极具有小于第一电极的横向尺寸的横向尺寸。 导电硬掩模覆盖在第二电极上并且与第二电极电连通。 导电硬掩模具有基本上等于第一电极的横向尺寸的横向尺寸。 导电接触元件与导电硬掩模电连通。

    Magnetoresistive random access memory devices and methods for fabricating the same
    9.
    发明授权
    Magnetoresistive random access memory devices and methods for fabricating the same 有权
    磁阻随机存取存储器件及其制造方法

    公开(公告)号：US07169622B2

    公开(公告)日：2007-01-30

    申请号：US10912979

    申请日：2004-08-05

    申请人： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Clarence J. Tracy

    发明人： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Clarence J. Tracy

    IPC分类号： H01L21/00

    CPC分类号： G11C11/16 ,  B82Y10/00 ,  H01L27/228

    摘要： Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.

    摘要翻译： 制造磁阻随机存取存储器单元和用于磁阻随机存取存储单元的结构开始于提供其中形成有晶体管的衬底。 形成电耦合到晶体管的接触元件，并且电介质材料沉积在由接触元件部分界定的区域内。 在电介质材料内形成数字线，数字线覆盖接触元件的一部分。 导电层形成在数字线上方并与接触元件电连通。

    Magnetic tunnel junction memory and method with etch-stop layer
    10.
    发明授权
    Magnetic tunnel junction memory and method with etch-stop layer 有权
    磁隧道结记忆和具有蚀刻停止层的方法

    公开(公告)号：US07445943B2

    公开(公告)日：2008-11-04

    申请号：US11584411

    申请日：2006-10-19

    申请人： Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

    发明人： Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

    IPC分类号： H01L21/00

    CPC分类号： H01L43/12

    摘要： Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.

    摘要翻译： 提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。 该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层 ，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及 位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。 在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。 获得了提高的产量和性能。