摘要:
A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielectric material separates the first electrode form the second electrodes and also separates the second electrodes. Each second electrode forms an individual memory cell associated with the first electrode. The memory cell assembly can be made by, first, forming a first electrode over a substrate. A second electrode layer is formed over the first electrode. The second electrode layer includes two or more second electrodes. A dielectric material is formed between the first electrode and the second electrodes and between the second electrodes.
摘要:
A method of forming a conductive plug in an interlevel dielectric includes forming a lower dielectric layer over a semiconductor substrate. A first etch mask is formed over the lower dielectric layer and is patterned using a reticle. A first etch is applied through an opening in the first etch mask to form an opening in the lower dielectric layer. A lower conductor is formed in the opening in the lower dielectric layer. A conducting layer is formed over the lower dielectric layer and the lower conductor. A second etch mask is formed over the conducting layer and is patterned using the reticle. A second etch is applied through an opening in the second etch mask to form a contact pad from an unetched portion of the conducting layer. An upper dielectric layer is formed over the lower dielectric layer and the contact pad. A third etch mask is formed over the upper dielectric layer and is patterned using the reticle. A third etch is applied through an opening in the third etch mask to form an opening in the upper dielectric layer. An upper conductor is formed in the opening in the upper dielectric layer. As a result, the conductive plug includes the upper and lower conductors and the contact pad, and the interlevel dielectric includes the upper and lower dielectric layers.
摘要:
A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over the two adjacent silicon active regions. The metal layer is then reacted with the silicon active regions to form a metal silicide on each silicon active region. This silicide reaction also forms silicide stringers extending from each silicon active region. Finally, at least part of each silicide stringer is removed. During the formation of the silicide stringers at least one silicide stringer may be formed which bridges the metal silicide over one of the silicon regions and the metal silicide over the other silicon region. In such circumstances, the removal process may, for example, break the silicide stringer and electrically decouple the two silicon regions. The two silicon active regions may, for example, be a gate electrode and an adjacet source/drain region. As another example, the two adjacent active regions may be two nearby polysilicon lines.
摘要:
A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a first dopant to form a doped polysilicon layer. Portions of the doped polysilicon layer are then removed to form at least one gate electrode. Active regions of the substrate adjacent the gate electrode are implanted with a second dopant to form source/drain regions in the substrate. In this manner, the implant used to form the source/drain regions may be decoupled from the implant used to form the gate electrode. This, for example, allows for shallower source/drain regions to be formed without the formation of the depletion layer in the gate electrode.
摘要:
One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first dopant material. A halo region is formed in the substrate under the spacer and adjacent to the active region using a second dopant material of a conductivity type different than the first dopant material. The halo region may be formed by implanting the second dopant region into the substrate at an angle substantially less than 90° relative to a surface of the substrate. A portion of the spacer is then removed and a lightly-doped region is formed in the substrate adjacent to the active region and the gate electrode and shallower than the halo region using a third dopant material of a same conductivity type as the first dopant material.
摘要:
One method of forming a semiconductor device includes forming a gate electrode on a substrate and then forming a spacer adjacent to a sidewall of the gate electrode. An active region is formed in the substrate adjacent to the spacer and spaced apart from the gate electrode using a first dopant material of a first conductivity type. A protecting layer is formed over the active region and adjacent to the spacer. At least a portion of the spacer is then removed to form an opening between the protecting layer and the gate electrode. In some instances, the spacer may be formed by independent deposition of two different materials (e.g., silicon nitride and silicon dioxide), one of which can be selectively removed with respect to the other. A lightly-doped region is formed in the substrate adjacent to the gate electrode using a second dopant material of the first conductivity type. This lightly-doped region may be formed, for example, prior to formation of the spacer, between the formation of two portions of the spacer, or after removing at least a portion of the spacer. A halo region is formed through the opening resulting from removing a portion of the spacer. The halo region is deeper in the substrate than the lightly-doped region and is adjacent to the active region. The halo region is formed using a third dopant material of a conductivity type different than the first conductivity type.
摘要:
A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first n-doped region in the NMOS active region. A first NMOS spacer is formed on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of a PMOS gate electrode. A second n-type dopant is selectively implanted into the NMOS active region using the first NMOS spacer as a mask. A p-type dopant is selectively implanted into a PMOS active region using the first PMOS spacer as a mask to form a first p-doped region in the PMOS active region. A second NMOS spacer and a second PMOS spacer are formed adjacent the first NMOS spacer and first PMOS spacer, respectively. A third n-type dopant is selectively implanted into the NMOS active region using the second NMOS spacer as a mask to form a third n-doped region deeper than the second n-doped region in the NMOS active region. A second p-type dopant is selectively implanted into the PMOS active region using the second PMOS spacer as a mask to form a second p-doped region in the PMOS active region deeper than the first p-doped region.
摘要:
A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate electrode formed at a design width and at a first line spacing similar to the line spacing of a dense transistor. One or more electrical properties the transistor of the first test structure is measured. A second test structure is formed on a second substrate portion. The second test structure includes a transistor having a gate electrode formed at the same design width as the transistor of the first test structure and at a second line spacing greater than the first line spacing. One or more electrical properties of the transistor of the second test structure are measured. Using the measured one or more electrical properties, one or more relationships are developed between the measured one or more electrical properties and the transistors at the first line spacing and the second line spacing.
摘要:
Semiconductor devices having one or more asymmetric background dopant regions and methods of fabrication thereof are provided. The asymmetric background dopant regions may be formed using a patterned mask with wider openings than conventional masks while substantially maintaining device performance. This can, for example, facilitate the fabrication process and allow greater flexibility in the choice of photolithography tools.
摘要:
A semiconductor device having an elevated gate electrode and elevated active regions and a process for manufacturing such a device is disclosed. In accordance with one embodiment a semiconductor device is formed by forming a gate insulating layer over a substrate and forming a photoresist block over the gate insulating layer. First portions of the gate insulating layer and first portions of the substrate adjacent the photoresist block are then removed to form a first elevated substrate region under the gate insulating layer and photoresist block. Edge portions of the photoresist block are then removed. Second portions of the gate insulating layer and portions of the first elevated substrate region adjacent the photoresist block are then removed to form second elevated substrate regions adjacent the photoresist block, and a dopant is implanted into the second elevated substrate regions to form source/drain regions, and the photoresist block is used to form a gate electrode. In accordance with another embodiment a semiconductor device is formed substantially as above, but the dopant is implanted at an angle relative to the substrate surface.