公开(公告)号：US6110786A

公开(公告)日：2000-08-29

申请号：US61409

申请日：1998-04-16

申请人： Mark I. Gardner ,  Jon Cheek ,  John Bush

发明人： Mark I. Gardner ,  Jon Cheek ,  John Bush

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/66636 ,  H01L29/78

摘要： A semiconductor device having an elevated gate electrode and elevated active regions and a process for manufacturing such a device is disclosed. In accordance with one embodiment a semiconductor device is formed by forming a gate insulating layer over a substrate and forming a photoresist block over the gate insulating layer. First portions of the gate insulating layer and first portions of the substrate adjacent the photoresist block are then removed to form a first elevated substrate region under the gate insulating layer and photoresist block. Edge portions of the photoresist block are then removed. Second portions of the gate insulating layer and portions of the first elevated substrate region adjacent the photoresist block are then removed to form second elevated substrate regions adjacent the photoresist block, and a dopant is implanted into the second elevated substrate regions to form source/drain regions, and the photoresist block is used to form a gate electrode. In accordance with another embodiment a semiconductor device is formed substantially as above, but the dopant is implanted at an angle relative to the substrate surface.

摘要翻译： 公开了一种具有升高的栅电极和升高的有源区的半导体器件及其制造方法。 根据一个实施例，通过在衬底上形成栅极绝缘层并在栅极绝缘层上形成光致抗蚀剂阻挡层来形成半导体器件。 然后去除栅极绝缘层的第一部分和与光致抗蚀剂嵌段相邻的基板的第一部分，以在栅极绝缘层和光致抗蚀剂阻挡块下方形成第一升高的基板区域。 然后去除光致抗蚀剂块的边缘部分。 然后去除栅极绝缘层的第二部分和邻近光致抗蚀剂阻挡块的第一升高的衬底区域的部分，以形成与光致抗蚀剂阻挡层相邻的第二升高的衬底区域，并且将掺杂剂注入第二升高的衬底区域以形成源极/漏极区域 ，并且光致抗蚀剂块用于形成栅电极。 根据另一个实施例，基本上如上所述形成半导体器件，但掺杂剂以相对于衬底表面成一角度注入。

公开(公告)号：US06638829B1

公开(公告)日：2003-10-28

申请号：US09199960

申请日：1998-11-25

申请人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

发明人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/28079 ,  H01L29/66545

摘要： A semiconductor structure and a process for its manufacture. A metal gate electrode is formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions.

摘要翻译： 半导体结构及其制造方法。 金属栅电极形成在半导体衬底上，栅极位于氮化物衬垫之间。 轻掺杂漏极区和源/漏区设置在衬底中并与电极和间隔物对准。 硅化物接触层设置在源/漏区上的衬底上的外延层上。

公开(公告)号：US06417539B2

公开(公告)日：2002-07-09

申请号：US09128864

申请日：1998-08-04

申请人： Mark I. Gardner ,  Derick J. Wristers ,  Jon Cheek

发明人： Mark I. Gardner ,  Derick J. Wristers ,  Jon Cheek

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielectric material separates the first electrode form the second electrodes and also separates the second electrodes. Each second electrode forms an individual memory cell associated with the first electrode. The memory cell assembly can be made by, first, forming a first electrode over a substrate. A second electrode layer is formed over the first electrode. The second electrode layer includes two or more second electrodes. A dielectric material is formed between the first electrode and the second electrodes and between the second electrodes.

摘要翻译： 存储单元组件包括衬底，第一电极和第二电极层。 第一电极设置在衬底上，并且第二电极层设置在第一电极上。 第二电极层包括两个或更多个第二电极。 电介质材料将第一电极与第二电极分开，并分离第二电极。 每个第二电极形成与第一电极相关联的单个存储单元。 存储单元组件可以通过首先在衬底上形成第一电极来制造。 在第一电极上形成第二电极层。 第二电极层包括两个或更多个第二电极。 在第一电极和第二电极之间以及第二电极之间形成电介质材料。

公开(公告)号：US5970349A

公开(公告)日：1999-10-19

申请号：US139179

申请日：1998-08-24

申请人： Jon Cheek ,  Mark I. Gardner ,  Michael Duane

发明人： Jon Cheek ,  Mark I. Gardner ,  Michael Duane

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/266

CPC分类号： H01L29/66659 ,  H01L29/1083

摘要： Semiconductor devices having one or more asymmetric background dopant regions and methods of fabrication thereof are provided. The asymmetric background dopant regions may be formed using a patterned mask with wider openings than conventional masks while substantially maintaining device performance. This can, for example, facilitate the fabrication process and allow greater flexibility in the choice of photolithography tools.

摘要翻译： 提供具有一个或多个不对称背景掺杂剂区域的半导体器件及其制造方法。 可以使用具有比常规掩模更宽的开口的图案化掩模来形成不对称背景掺杂区域，同时基本上保持器件性能。 例如，这可以促进制造工艺并且允许在光刻工具的选择中具有更大的灵活性。

公开(公告)号：US06674135B1

公开(公告)日：2004-01-06

申请号：US09199666

申请日：1998-11-25

申请人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

发明人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

IPC分类号： H01L2976

CPC分类号： H01L21/28202 ,  H01L21/28017 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628

摘要： A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions. The metal gate electrode is aligned using a polysilicon alignment structure, which permits high temperature processing before the metal is deposited.

摘要翻译： 半导体结构及其制造方法。 第一和第二栅极电介质层形成在氮化物间隔物之间​​的半导体衬底上，并且在栅极电介质层上形成金属栅电极。 轻掺杂漏极区和源/漏区设置在衬底中并与电极和间隔物对准。 硅化物接触层设置在源/漏区上的衬底上的外延层上。 使用多晶硅取向结构对准金属栅电极，其可以在金属沉积之前进行高温处理。

公开(公告)号：US6104077A

公开(公告)日：2000-08-15

申请号：US60160

申请日：1998-04-14

申请人： Mark I. Gardner ,  Derick Wristers ,  Jon Cheek

发明人： Mark I. Gardner ,  Derick Wristers ,  Jon Cheek

IPC分类号： H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor device having a gate electrode with a sidewall air gap is provided. In accordance with this embodiment, at least one gate electrode is formed over a substrate. A spacer is then formed adjacent an upper sidewall portion of the gate electrode such that an open area is left beneath the spacer. Next, a dielectric layer is formed over the spacer and the gate electrode, thereby leaving an air gap in the open area. In accordance with one aspect of the invention, both the gate electrode and the spacer adjacent the gate electrode are formed from polysilicon. This, for example, allows the formation of a wider contact area to the gate electrode.

摘要翻译： 提供具有侧壁气隙的栅电极的半导体器件。 根据本实施例，在衬底上形成至少一个栅电极。 然后在栅电极的上侧壁部分附近形成间隔件，使得开口区域留在间隔件下方。 接下来，在间隔物和栅电极之上形成介电层，从而在开放区域中留下空隙。 根据本发明的一个方面，栅电极和与栅电极相邻的间隔物均由多晶硅形成。 例如，这允许形成更宽的与栅电极的接触面积。

公开(公告)号：US5913116A

公开(公告)日：1999-06-15

申请号：US780455

申请日：1997-01-08

申请人： Mark I. Gardner ,  Jon Cheek

发明人： Mark I. Gardner ,  Jon Cheek

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864

摘要： In semiconductor device fabrication process, an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. In the fabrication process, a gate electrode having a sidewall adjacent an active region is formed on a substrate and a doped spacer layer having a dopant disposed therein is formed over the substrate and gate electrode. A portion of the spacer layer is then removed to form a spacer on the sidewall of the gate electrode. The dopant in the spacer is diffused into the substrate to form a lightly-doped region in the active region of the substrate. The lightly-doped region may form an LDD region of an LDD structure.

摘要翻译： 在半导体器件制造工艺中，半导体器件的有源区通过从侧壁间隔物扩散出来形成。 在制造工艺中，在衬底上形成具有邻近有源区的侧壁的栅电极，并且在衬底和栅电极上形成其中具有掺杂剂的掺杂间隔层。 然后去除间隔层的一部分以在栅电极的侧壁上形成间隔物。 间隔物中的掺杂剂扩散到衬底中以在衬底的有源区中形成轻掺杂区域。 轻掺杂区域可以形成LDD结构的LDD区域。

公开(公告)号：US06979878B1

公开(公告)日：2005-12-27

申请号：US09217213

申请日：1998-12-21

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

IPC分类号： H01L21/762 ,  H01L29/36

CPC分类号： H01L21/76237

摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.

摘要翻译： 一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。 该方法包括在半导体衬底上形成电介质掩模层。 然后通过掩模层形成开口。 在开口内的掩模层的侧壁上形成一对电介质隔离物。 然后在电介质间隔物之间​​的半导体衬底中蚀刻沟槽。 然后在沟槽的壁和基底上热生长第一介电层。 将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。 间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。 然后将硅原子和/或势垒原子（例如氮原子）注入非常靠近沟槽隔离结构的有源区的多个区域中。

公开(公告)号：US06743688B1

公开(公告)日：2004-06-01

申请号：US09002964

申请日：1998-01-05

申请人： Mark I. Gardner ,  H. James Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. James Fulford ,  Charles E. May

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/265 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/78 ,  Y10S438/981

摘要： A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.

摘要翻译： 具有第一厚度和第二厚度的栅极氧化物的半导体器件通过首先用氮离子注入半导体衬底的栅极区域的一部分，然后在栅极区域上形成栅极氧化物来形成。 优选地，通过将​​栅极区域暴露于氧气环境来生长栅极氧化物。 氮注入抑制氧气环境中的二氧化硅生长速率。 因此，具有植入氮原子的栅极区域的部分将生长或形成诸如SiO 2的栅极氧化物层，其比栅极区域较少注入或未注入氮原子的部分更薄。 可以沉积栅极氧化物层而不是生长栅极氧化物层。 在形成栅极氧化物层之后，将多晶硅沉积到栅极氧化物上。 然后可以注入半导体衬底以形成掺杂的漏极和源极区域。 然后可以将间隔物放置在漏极和源极区域上并且邻近栅极的侧壁的端部。

公开(公告)号：US06451657B1

公开(公告)日：2002-09-17

申请号：US09781044

申请日：2001-02-08

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

IPC分类号： H01L21336

CPC分类号： H01L21/28132 ,  Y10S257/90

摘要： A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.

摘要翻译： 公开了一种用于制造具有小于使用普通光刻技术可分辨长度的沟道长度的晶体管的工艺。 在轻掺杂的半导体衬底上形成栅氧化层。 然后在栅极氧化物层上沉积栅极导体层。 栅极导体层的上表面包括由间隔开的一对目标区域横向限定的未来导体区域，其中间隔开的一对目标区域之间的横向距离优选地以光刻阈值选择。 将氮气注入到间隔开的一对目标区域中，以在栅极导体层内形成间隔开的一对含氮区域，从而在栅极导体层中限定无氮区域。 热退火降低了无氮区域的宽度。 然后在整个半导体拓扑上生长可变厚度的氧化物层，并进行各向异性蚀刻，以在较宽的无氮区域上形成氧化物掩模。 然后去除不被氧化物掩模覆盖的栅极导体层的部分，留下宽度窄的无氮区域作为宽度低于光刻阈值的栅极导体。