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    Programming in memory devices using source bitline voltage bias
    7.
    发明授权
    Programming in memory devices using source bitline voltage bias 有权
    使用源位线电压偏置对存储器件进行编程

    公开(公告)号：US07746698B2

    公开(公告)日：2010-06-29

    申请号：US11956032

    申请日：2007-12-13

    申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/12

    摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

    摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

    PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS
    8.
    发明申请
    PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS 有权
    使用源电压偏置在存储器件中编程

    公开(公告)号：US20090154246A1

    公开(公告)日：2009-06-18

    申请号：US11956032

    申请日：2007-12-13

    申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/12

    摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

    摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

    Programming a memory device
    9.
    发明授权
    Programming a memory device 有权
    编程内存设备

    公开(公告)号：US07269067B2

    公开(公告)日：2007-09-11

    申请号：US11174560

    申请日：2005-07-06

    申请人： Shankar Sinha ,  Zhizheng Liu ,  Yi He

    发明人： Shankar Sinha ,  Zhizheng Liu ,  Yi He

    IPC分类号： G11C11/34

    CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias to a source region associated with the memory cell and/or applying a negative bias to a substrate region associated with the memory cell.

    摘要翻译： 一种对非易失性存储器件中的存储器单元进行编程的方法包括：将第一电压施加到与存储器单元相关联的控制栅极，并将第二电压施加到与存储器单元相关联的漏极区域。 该方法还包括向与存储器单元相关联的源极区域施加正偏压和/或将负偏压施加到与存储器单元相关联的衬底区域。

    Barrier region underlying source/drain regions for dual-bit memory devices
    10.
    发明授权
    Barrier region underlying source/drain regions for dual-bit memory devices 有权
    用于双位存储器件的源极/漏极区域的屏障区域

    公开(公告)号：US09171936B2

    公开(公告)日：2015-10-27

    申请号：US11634777

    申请日：2006-12-06

    申请人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    发明人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L27/115 ,  H01L29/792

    CPC分类号： H01L29/66833 ,  H01L21/26506 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792

    摘要： One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

    摘要翻译： 本发明的一个实施例涉及一种存储单元。 存储单元包括衬底和布置在衬底上的层叠栅极结构，其中堆叠栅极结构包括适于存储至少一位数据的电荷捕获介电层。 存储单元还包括衬底中的源极和漏极，其中源极和漏极设置在堆叠的栅极结构的相对侧。 阻挡区域基本上设置在源极或漏极下方并且包括惰性物质。 还公开了其他实施例。