专利检索 ap:("Marko Radosavljevic" OR "Suman Datta" OR "Brian S. Doyle" OR "Jack Kavalieros" OR "Justin K. Brask" OR "Mark L. Doczy" OR "Amian Majumdar" OR "Robert S. Chau") AND inv:"Marko Radosavljevic" 第 1 页

1.

发明申请
FIELD EFFECT TRANSISTOR WITH METAL SOURCE/DRAIN REGIONS 有权
标题翻译：具有金属源/漏区的场效应晶体管

公开(公告)号：US20090325350A1

公开(公告)日：2009-12-31

申请号：US12114227

申请日：2008-05-02

申请人： Marko Radosavljevic , Suman Datta , Brian S. Doyle , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Amian Majumdar , Robert S. Chau

发明人： Marko Radosavljevic , Suman Datta , Brian S. Doyle , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Amian Majumdar , Robert S. Chau

IPC分类号： H01L21/762 , H01L21/336

CPC分类号： H01L29/41791 , H01L21/3141 , H01L23/485 , H01L29/66636 , H01L29/7843 , H01L29/785 , H01L29/78621 , H01L29/78681 , H01L29/78684 , H01L2029/7858 , H01L2924/0002 , H01L2924/00

摘要： A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

摘要翻译： 一种半导体器件，包括形成在形成在半导体膜上的栅极电介质层上的栅电极。一对源极/漏极区域形成在栅电极的相对侧上的沟道区域附近。源极和漏极区域各自包括与半导体沟道相邻并与其接触的半导体部分和与半导体部分相邻并与其接触的金属部分。

2.

发明授权
Field effect transistor with metal source/drain regions 有权
标题翻译：具有金属源极/漏极区域的场效应晶体管

公开(公告)号：US07879675B2

公开(公告)日：2011-02-01

申请号：US12114227

申请日：2008-05-02

申请人： Marko Radosavljevic , Suman Datta , Brian S. Doyle , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Amian Majumdar , Robert S. Chau

发明人： Marko Radosavljevic , Suman Datta , Brian S. Doyle , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Amian Majumdar , Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L29/41791 , H01L21/3141 , H01L23/485 , H01L29/66636 , H01L29/7843 , H01L29/785 , H01L29/78621 , H01L29/78681 , H01L29/78684 , H01L2029/7858 , H01L2924/0002 , H01L2924/00

摘要： A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

摘要翻译： 一种半导体器件，包括形成在形成在半导体膜上的栅极电介质层上的栅电极。一对源极/漏极区域形成在栅电极的相对侧上的沟道区域附近。源极和漏极区域各自包括与半导体沟道相邻并与其接触的半导体部分和与半导体部分相邻并与其接触的金属部分。

3.

发明申请
Block Contact Architectures for Nanoscale Channel Transistors 有权
标题翻译：用于纳米级晶体管的块式触点架构

公开(公告)号：US20080258207A1

公开(公告)日：2008-10-23

申请号：US11855823

申请日：2007-09-14

申请人： Marko Radosavljevic , Amlan Majumdar , Brian S. Doyle , Jack Kavalieros , Mark L. Doczy , Justin K. Brask , Uday Shah , Suman Datta , Robert S. Chau

发明人： Marko Radosavljevic , Amlan Majumdar , Brian S. Doyle , Jack Kavalieros , Mark L. Doczy , Justin K. Brask , Uday Shah , Suman Datta , Robert S. Chau

IPC分类号： H01L29/786

CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/7851 , H01L29/78681 , H01L29/78684 , H01L2029/7858

摘要： A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

摘要翻译： 一种用于纳米尺度通道器件的接触结构，其具有耦合到具有多个平行半导体器件的器件的源极或漏极区域之间并具有接触结构的接触结构。接触结构能够接触具有亚光刻间距的平行半导体本体。

4.

发明授权
Forming field effect transistors from conductors 有权
标题翻译：从导体形成场效应晶体管

公开(公告)号：US07390947B2

公开(公告)日：2008-06-24

申请号：US11037512

申请日：2005-01-18

申请人： Amlan Majumdar , Justin K. Brask , Marko Radosavljevic , Suman Datta , Brian S. Doyle , Mark L. Doczy , Jack Kavalieros , Matthew V. Metz , Robert S. Chau , Uday Shah , James Blackwell

发明人： Amlan Majumdar , Justin K. Brask , Marko Radosavljevic , Suman Datta , Brian S. Doyle , Mark L. Doczy , Jack Kavalieros , Matthew V. Metz , Robert S. Chau , Uday Shah , James Blackwell

IPC分类号： H01L29/12

CPC分类号： B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/1606 , H01L51/0048 , H01L51/0052 , H01L51/0541 , H01L51/0545 , Y10S977/701 , Y10S977/938

摘要： A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the substrate may act as a back gate.

摘要翻译： 诸如碳纳米管晶体管的纳米管晶体管可以形成有顶栅电极和间隔开的源极和漏极。沿晶体管从源极到漏极的导通由栅电极控制。栅电极底部至少有两个纳米管。在一些实施例中，衬底可用作背栅。

5.

发明授权
Block contact architectures for nanoscale channel transistors 有权
标题翻译：用于纳米尺度通道晶体管的块式接触结构

公开(公告)号：US07898041B2

公开(公告)日：2011-03-01

申请号：US11855823

申请日：2007-09-14

申请人： Marko Radosavljevic , Amlan Majumdar , Brian S. Doyle , Jack Kavalieros , Mark L. Doczy , Justin K. Brask , Uday Shah , Suman Datta , Robert S. Chau

发明人： Marko Radosavljevic , Amlan Majumdar , Brian S. Doyle , Jack Kavalieros , Mark L. Doczy , Justin K. Brask , Uday Shah , Suman Datta , Robert S. Chau

IPC分类号： H01L27/01

CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/7851 , H01L29/78681 , H01L29/78684 , H01L2029/7858

摘要： A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

摘要翻译： 一种用于纳米尺度通道器件的接触结构，其具有耦合到具有多个平行半导体器件的器件的源极或漏极区域之间并具有接触结构的接触结构。接触结构能够接触具有亚光刻间距的平行半导体本体。

6.

发明授权
Block contact architectures for nanoscale channel transistors 有权

公开(公告)号：US07279375B2

公开(公告)日：2007-10-09

申请号：US11173866

申请日：2005-06-30

申请人： Marko Radosavljevic , Amlan Majumdar , Brian S. Doyle , Jack Kavalieros , Mark L. Doczy , Justin K. Brask , Uday Shah , Suman Datta , Robert S. Chau

发明人： Marko Radosavljevic , Amlan Majumdar , Brian S. Doyle , Jack Kavalieros , Mark L. Doczy , Justin K. Brask , Uday Shah , Suman Datta , Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/7851 , H01L29/78681 , H01L29/78684 , H01L2029/7858

摘要： A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

7.

发明授权
Method for fabricating transistor with thinned channel 有权
标题翻译：用稀疏通道制造晶体管的方法

公开(公告)号：US07858481B2

公开(公告)日：2010-12-28

申请号：US11154138

申请日：2005-06-15

申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic

发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

摘要翻译： 描述了制造具有减薄沟道区的MOS晶体管的方法。在去除虚拟栅极之后蚀刻沟道区。源极和漏极区域具有相对较低的电阻。

8.

发明授权
Method for fabricating transistor with thinned channel 有权

公开(公告)号：US09337307B2

公开(公告)日：2016-05-10

申请号：US12949696

申请日：2010-11-18

申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic

发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic

IPC分类号： H01L29/66 , H01L29/423 , H01L29/78

CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

9.

发明申请
METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL 审中-公开
标题翻译：用于制造具有薄型通道的晶体管的方法

公开(公告)号：US20110062520A1

公开(公告)日：2011-03-17

申请号：US12949696

申请日：2010-11-18

申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic

发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic

IPC分类号： H01L29/786

CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

摘要翻译： 描述了制造具有减薄沟道区的MOS晶体管的方法。在去除虚拟栅极之后蚀刻沟道区。源极和漏极区域具有相对较低的电阻。

10.

发明申请
Reducing Ambipolar Conduction in Carbon Nanotube Transistors 审中-公开
标题翻译：降低碳纳米管晶体管中的双极传导

公开(公告)号：US20090159872A1

公开(公告)日：2009-06-25

申请号：US12359479

申请日：2009-01-26

申请人： Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Marko Radosavljevic , Amlan Majumdar , Justin K. Brask , Robert S. Chau

发明人： Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Marko Radosavljevic , Amlan Majumdar , Justin K. Brask , Robert S. Chau

IPC分类号： H01L29/08

CPC分类号： H01L51/102 , B82Y10/00 , H01L51/0048 , H01L51/0052 , H01L51/0545 , H01L51/105

摘要： Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.

摘要翻译： 通过形成金属的栅电极，可以在碳纳米管晶体管中减少双极传导。可以形成具有与栅电极不同的功函数的金属侧壁间隔物以支撑金属栅电极。

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