公开(公告)号：US08445956B2

公开(公告)日：2013-05-21

申请号：US12039395

申请日：2008-02-28

申请人： Martin Poelzl ,  Walter Rieger ,  Markus Zundel

发明人： Martin Poelzl ,  Walter Rieger ,  Markus Zundel

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/76877 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate.

摘要翻译： 一种半导体器件和半导体器件的制造方法。 一个实施例提供了具有与有源区域接壤的有源区和边缘区的半导体衬底。 边缘区域中的间隔层在选定位置断裂，并且使用公共过程在有源区域中移除间隔层的至少一部分。 选择位置使得半导体台面结构的至少一部分被暴露，并且边缘区域中的间隔层被破坏到导电层而不是破坏到半导体衬底。

公开(公告)号：US20080214004A1

公开(公告)日：2008-09-04

申请号：US12039395

申请日：2008-02-28

申请人： Martin Poelzl ,  Walter Rieger ,  Markus Zundel

发明人： Martin Poelzl ,  Walter Rieger ,  Markus Zundel

IPC分类号： H01L21/02 ,  H01L29/86

CPC分类号： H01L21/76877 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate.

摘要翻译： 一种半导体器件和半导体器件的制造方法。 一个实施例提供了具有与有源区域接壤的有源区和边缘区的半导体衬底。 边缘区域中的间隔层在选定位置断裂，并且使用公共过程在有源区域中移除间隔层的至少一部分。 选择位置使得半导体台面结构的至少一部分被暴露，并且边缘区域中的间隔层被破坏到导电层而不是破坏到半导体衬底。

公开(公告)号：US07414286B2

公开(公告)日：2008-08-19

申请号：US11513969

申请日：2006-08-31

申请人： Franz Hirler ,  Martin Poelzl ,  Markus Zundel ,  Rudolf Zelsacher

发明人： Franz Hirler ,  Martin Poelzl ,  Markus Zundel ,  Rudolf Zelsacher

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734

摘要： A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The electrode structure is electrically insulated from the semiconductor body by an insulation structure. The electrode structure has a gate electrode structure and a field electrode structure arranged below the gate electrode structure and electrically insulated from the latter. There is provided between the gate electrode structure and the field electrode structure a shielding structure for reducing the capacitive coupling between the gate electrode structure and the field electrode structure.

摘要翻译： 公开了一种具有半导体本体的沟槽晶体管，其中沟槽结构和嵌入沟槽结构中的电极结构被公开。 电极结构通过绝缘结构与半导体本体电绝缘。 电极结构具有栅电极结构和场电极结构，其布置在栅电极结构的下方并与之电绝缘。 在栅电极结构和场电极结构之间设置有用于减小栅电极结构和场电极结构之间的电容耦合的屏蔽结构。

公开(公告)号：US20070114600A1

公开(公告)日：2007-05-24

申请号：US11513969

申请日：2006-08-31

申请人： Franz Hirler ,  Martin Poelzl ,  Markus Zundel ,  Rudolf Zelsacher

发明人： Franz Hirler ,  Martin Poelzl ,  Markus Zundel ,  Rudolf Zelsacher

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734

摘要： A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The electrode structure is electrically insulated from the semiconductor body by an insulation structure. The electrode structure has a gate electrode structure and a field electrode structure arranged below the gate electrode structure and electrically insulated from the latter. There is provided between the gate electrode structure and the field electrode structure a shielding structure for reducing the capacitive coupling between the gate electrode structure and the field electrode structure.

摘要翻译： 公开了一种具有半导体本体的沟槽晶体管，其中沟槽结构和嵌入沟槽结构中的电极结构被公开。 电极结构通过绝缘结构与半导体本体电绝缘。 电极结构具有栅电极结构和场电极结构，其布置在栅电极结构的下方并与之电绝缘。 在栅电极结构和场电极结构之间设置有用于减小栅电极结构和场电极结构之间的电容耦合的屏蔽结构。

公开(公告)号：US07790550B2

公开(公告)日：2010-09-07

申请号：US12186242

申请日：2008-08-05

申请人： Franz Hirler ,  Martin Poelzl ,  Markus Zundel ,  Rudolf Zelsacher

发明人： Franz Hirler ,  Martin Poelzl ,  Markus Zundel ,  Rudolf Zelsacher

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734

摘要： A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The electrode structure is electrically insulated from the semiconductor body by an insulation structure. The electrode structure has a gate electrode structure and a field electrode structure arranged below the gate electrode structure and electrically insulated from the latter. There is provided between the gate electrode structure and the field electrode structure a shielding structure for reducing the capacitive coupling between the gate electrode structure and the field electrode structure.

摘要翻译： 公开了一种具有半导体本体的沟槽晶体管，其中沟槽结构和嵌入沟槽结构中的电极结构被公开。 电极结构通过绝缘结构与半导体本体电绝缘。 电极结构具有栅电极结构和场电极结构，其布置在栅电极结构的下方并与之电绝缘。 在栅电极结构和场电极结构之间设置有用于减小栅电极结构和场电极结构之间的电容耦合的屏蔽结构。

公开(公告)号：US20090206401A1

公开(公告)日：2009-08-20

申请号：US12186242

申请日：2008-08-05

申请人： Franz Hirler ,  Martin Poelzl ,  Markus Zundel ,  Rudolf Zelsacher

发明人： Franz Hirler ,  Martin Poelzl ,  Markus Zundel ,  Rudolf Zelsacher

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734

摘要： A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The electrode structure is electrically insulated from the semiconductor body by an insulation structure. The electrode structure has a gate electrode structure and a field electrode structure arranged below the gate electrode structure and electrically insulated from the latter. There is provided between the gate electrode structure and the field electrode structure a shielding structure for reducing the capacitive coupling between the gate electrode structure and the field electrode structure.

摘要翻译： 公开了一种具有半导体本体的沟槽晶体管，其中沟槽结构和嵌入沟槽结构中的电极结构被公开。 电极结构通过绝缘结构与半导体本体电绝缘。 电极结构具有栅电极结构和场电极结构，其布置在栅电极结构的下方并与之电绝缘。 在栅电极结构和场电极结构之间设置有用于减小栅电极结构和场电极结构之间的电容耦合的屏蔽结构。

公开(公告)号：US08907340B2

公开(公告)日：2014-12-09

申请号：US13241627

申请日：2011-09-23

申请人： Franz Hirler ,  Walter Rieger ,  Lutz Goergens ,  Helmut Angerer ,  Gianmauro Pozzovivo ,  Markus Zundel

发明人： Franz Hirler ,  Walter Rieger ,  Lutz Goergens ,  Helmut Angerer ,  Gianmauro Pozzovivo ,  Markus Zundel

IPC分类号： H01L23/58 ,  H01L27/06 ,  B82Y10/00 ,  H01L27/22 ,  H01L43/06 ,  H01L29/778

CPC分类号： B82Y10/00 ,  H01L27/0617 ,  H01L27/22 ,  H01L29/7787 ,  H01L43/065

摘要： A semiconductor arrangement includes a semiconductor body and a semiconductor device, the semiconductor device including first and second load terminals arranged distant to each other in a first direction of the semiconductor body and a load path arranged in the semiconductor body between the first and second load terminals. The semiconductor arrangement further includes at least one Hall sensor arranged in the semiconductor body distant to the semiconductor device in a second direction perpendicular to the first direction. The Hall sensor includes two current supply terminals and two measurement terminals.

摘要翻译： 半导体装置包括半导体本体和半导体器件，所述半导体器件包括在所述半导体本体的第一方向上彼此远离布置的第一和第二负载端子以及布置在所述半导体本体中的所述第一和第二负载端子之间的负载路径 。 半导体装置还包括至少一个霍尔传感器，该霍尔传感器在垂直于第一方向的第二方向上布置在远离半导体器件的半导体本体中。 霍尔传感器包括两个电源端子和两个测量端子。

公开(公告)号：US08314447B2

公开(公告)日：2012-11-20

申请号：US12764669

申请日：2010-04-21

申请人： Franz Hirler ,  Walter Rieger ,  Markus Zundel

发明人： Franz Hirler ,  Walter Rieger ,  Markus Zundel

IPC分类号： H01L29/739

CPC分类号： H01L29/778 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7786

摘要： A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.

摘要翻译： 公开了包括横向HEMT的半导体和用于制造横向HEMT的方法。 在一个实施例中，横向HEMT具有衬底和第一层，其中第一层具有第一导电类型的半导体材料并且至少部分地布置在衬底上。 此外，横向HEMT具有第二层，其中第二层具有半导体材料并且至少部分地布置在第一层上。 此外，横向HEMT具有第三层，其中第三层具有与第一导电类型互补的第二导电类型的半导体材料，并且至少部分地布置在第一层中。

公开(公告)号：US07999287B2

公开(公告)日：2011-08-16

申请号：US12605751

申请日：2009-10-26

申请人： Markus Zundel ,  Franz Hirler ,  Walter Rieger

发明人： Markus Zundel ,  Franz Hirler ,  Walter Rieger

IPC分类号： H01L29/66

CPC分类号： H01L29/404 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： In one embodiment a lateral HEMT has a first layer, the first layer including a semiconducting material, and a second layer, the second layer including a semiconducting material and being at least partially arranged on the first layer. The lateral HEMT further has a passivation layer and a drift region, the drift region including a lateral width wd. The lateral HEMT further has at least one field plate, the at least one field plate being arranged at least partially on the passivation layer in a region of the drift region and including a lateral width wf, wherein wf

摘要翻译： 在一个实施例中，横向HEMT具有第一层，第一层包括半导体材料和第二层，第二层包括半导体材料并且至少部分地布置在第一层上。 横向HEMT还具有钝化层和漂移区域，漂移区域包括横向宽度wd。 横向HEMT还具有至少一个场板，所述至少一个场板至少部分地布置在所述漂移区域的区域中的钝化层上，并且包括横向宽度wf，其中wf

公开(公告)号：US20070093019A1

公开(公告)日：2007-04-26

申请号：US11527743

申请日：2006-09-26

申请人： Walter Rieger ,  Paul Ganitzer ,  Oliver Haeberlen ,  Franz Hirler ,  Markus Zundel ,  Rudolf Zelsacher ,  Erwin Bacher

发明人： Walter Rieger ,  Paul Ganitzer ,  Oliver Haeberlen ,  Franz Hirler ,  Markus Zundel ,  Rudolf Zelsacher ,  Erwin Bacher

IPC分类号： H01L21/8242 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397

摘要： Method for producing a connection electrode for two semiconductor zones arranged one above another The invention relates to a method for producing a connection electrode for a first semiconductor zone and a second semiconductor zone, which are arranged one above another and are doped complementarily with respect to one another, which method comprises the method steps of: producing a trench extending through the first semiconductor zone right into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench, applying a protective layer to one of the first and second semiconductor zones in the trench, producing a first connection zone in the other of the two semiconductor zones, which is not covered by the protective layer, by introducing dopant atoms into this other semiconductor zone via the trench, the connection zone being of the same conductivity type as said other semiconductor zone, but doped more highly, depositing an electrode layer at least onto the sidewalls and the bottom of the trench for the purpose of producing the connection electrode.

摘要翻译： 一种制造用于两个半导体区域的连接电极的方法本发明涉及一种用于制造用于第一半导体区域和第二半导体区域的连接电极的方法，所述连接电极被布置在另一个之上，并且相对于一个 另一方面，该方法包括以下方法步骤：产生通过第一半导体区域直接进入第二半导体区域的沟槽，使得第一半导体区域在沟槽的侧壁处未被覆盖，并且至少覆盖第二半导体区域 在沟槽的底部，在沟槽中的第一和第二半导体区域中的一个上施加保护层，在两个半导体区域中的另一个半导体区域中的第一连接区域中，未被保护层覆盖，通过引入掺杂剂 原子通过沟槽进入该另一半导体区，连接区具有相同的导电性 类型作为所述另一半导体区，但是掺杂更高，至少在沟槽的侧壁和底部上沉积电极层以产生连接电极。