公开(公告)号：US20060023556A1

公开(公告)日：2006-02-02

申请号：US11189018

申请日：2005-07-26

申请人： Martin Versen ,  Martin Perner

发明人： Martin Versen ,  Martin Perner

IPC分类号： G11C8/00

CPC分类号： G11C7/20 ,  G11C11/401 ,  G11C29/24

摘要： An integrated semiconductor memory has regular row and column lines, which can be replaced with redundant row and column lines in the event of a fault. Following initialization of the memory cells with an initialization data item, a data generator circuit writes an identification data item to the memory cells along a regular row or column line. A faulty regular row or column line is replaced with the associated redundant row or column line. Next, the initialization data item is written to memory cells along sound regular row or column lines and the respective identification data item is written to the memory cells along a faulty regular row or column line. Faulty regular row or column lines have the same data value in their memory cells as the redundant row or column lines replacing them.

摘要翻译： 集成半导体存储器具有规则的行和列线，在故障的情况下可以用冗余的行和列线代替。 在利用初始化数据项初始化存储器单元之后，数据生成器电路沿着常规行或列线将识别数据项写入存储单元。 错误的常规行或列行将替换为关联的冗余行或列行。 接下来，按照声音规则行或列行将初始化数据项写入存储单元，并且将相应的标识数据项沿故障的规则行或列行写入存储单元。 故障的常规行或列行在其存储单元中具有与替换它们的冗余行或列行相同的数据值。

公开(公告)号：US07203106B2

公开(公告)日：2007-04-10

申请号：US11189018

申请日：2005-07-26

申请人： Martin Versen ,  Martin Perner

发明人： Martin Versen ,  Martin Perner

IPC分类号： G11C7/00

CPC分类号： G11C7/20 ,  G11C11/401 ,  G11C29/24

摘要： An integrated semiconductor memory has regular row and column lines, which can be replaced with redundant row and column lines in the event of a fault. Following initialization of the memory cells with an initialization data item, a data generator circuit writes an identification data item to the memory cells along a regular row or column line. A faulty regular row or column line is replaced with the associated redundant row or column line. Next, the initialization data item is written to memory cells along sound regular row or column lines and the respective identification data item is written to the memory cells along a faulty regular row or column line. Faulty regular row or column lines have the same data value in their memory cells as the redundant row or column lines replacing them.

摘要翻译： 集成半导体存储器具有规则的行和列线，在故障的情况下可以用冗余的行和列线代替。 在利用初始化数据项初始化存储器单元之后，数据生成器电路沿着常规行或列线将识别数据项写入存储单元。 错误的常规行或列行将替换为关联的冗余行或列行。 接下来，按照声音规则行或列行将初始化数据项写入存储单元，并且将相应的标识数据项沿故障的规则行或列行写入存储单元。 故障的常规行或列行在其存储单元中具有与替换它们的冗余行或列行相同的数据值。

公开(公告)号：US07385837B2

公开(公告)日：2008-06-10

申请号：US11241879

申请日：2005-09-30

申请人： Martin Perner

发明人： Martin Perner

IPC分类号： G11C11/00

CPC分类号： G11C11/005

摘要： A nonvolatile memory cell (1) can be integrated in space-saving fashion into a semiconductor circuit (10) intended for volatile storage with the aid of volatile memory cells (2). The memory cell (1) has a programmable component (3) having an electrical resistance that can be altered by reprogramming, and also first (8) and second switching elements (9), which switch a first current path (J1) or a second current path (J2) in conducting fashion upon activation of optionally a first (11) or a second word line (12). At least one of the two current paths leads via the programmable component (3). Potentials of two bit lines (21, 22) to which the memory cell (1) according to the invention is connected can be altered as a result of the first or the second current path (J1, J2) being activated temporarily. The memory cell (1) permanently stores an item of digital information and can be driven by word lines (11, 12) and bit lines (21, 22) such as are conventionally used in volatile semiconductor memories (10). The invention opens up the possibility of integrating volatile and nonvolatile memory cells into a common memory cell array.

摘要翻译： 借助于易失性存储器单元（2），非易失性存储单元（1）可以以节省空间的方式集成到旨在用于易失性存储的半导体电路（10）中。 存储单元（1）具有可通过重新编程改变的电阻的可编程组件（3），以及第一（8）和第二开关元件（9），其将第一电流路径（J 1）或 第二电流路径（J 2）在可选地第一（11）或第二字线（12）激活时以导通方式。 两个电流路径中的至少一个通过可编程组件（3）引出。 由于第一或第二电流路径（J 1，J 2）暂时被激活，可以改变与本发明的存储单元（1）连接的两个位线（21,22）的电位。 存储单元（1）永久地存储数字信息的项目，并且可以由诸如常规用于易失性半导体存储器（10）的字线（11,12）和位线（21,22）驱动。 本发明揭示了将易失性和非易失性存储单元集成到公共存储单元阵列中的可能性。

公开(公告)号：US07337284B2

公开(公告)日：2008-02-26

申请号：US11191141

申请日：2005-07-28

申请人： Martin Perner

发明人： Martin Perner

IPC分类号： G06F12/00

CPC分类号： G11C7/1006 ,  G11C11/4096 ,  G11C29/42

摘要： An integrated semiconductor memory includes a memory cell array having memory cells for storing a datum having a first and a second data value. An input datum present at a data terminal is stored multiply in the memory cells of the memory cell array. In order to read out the input datum, the multiply stored input data are fed to an evaluation circuit. The evaluation circuit generates, on the output side, an output datum having the data value that was stored more frequently in the memory cells used for multiple storage of the input datum than other data values. The integrated semiconductor memory thus makes it possible to reduce transfer errors when reading data into the memory cell array or reading data out of the memory cell array.

摘要翻译： 集成半导体存储器包括具有用于存储具有第一和第二数据值的数据的存储单元的存储单元阵列。 存在于数据终端的输入数据被乘法存储在存储单元阵列的存储单元中。 为了读取输入数据，乘法存储的输入数据被馈送到评估电路。 评估电路在输出侧产生具有比其他数据值更多地存储在用于多个存储输入数据的存储单元中的数据值的输出数据。 因此，集成半导体存储器使得可以在将数据读入存储单元阵列或从存储单元阵列读出数据时减少传输错误。

公开(公告)号：US07082513B2

公开(公告)日：2006-07-25

申请号：US10633996

申请日：2003-08-04

申请人： Dirk Fuhrmann ,  Martin Perner

发明人： Dirk Fuhrmann ,  Martin Perner

IPC分类号： G06F12/06

CPC分类号： G11C29/20 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4087 ,  G11C29/70 ,  G11C2029/1802 ,  G11C2029/3602

摘要： An integrated memory contains an addressing unit for addressing memory cells for a memory access on the basis of received addressing signals. An addressing calculation logic unit is connected to the addressing unit. The latter can be activated by a test mode signal for a test operation of the memory. The addressing calculation logic unit receives command signals and address signals for the test operation, calculates therefrom the addressing signals for the memory access and feeds the latter into the addressing unit. After an initialization with the loading of initial parameters, the command signals and address signals for the test operation are applied to the addressing calculation logic unit and read/write operations are carried out by an access controller. An integrated memory with implemented BIST hardware, in the case of which a comparatively high functionality and flexibility during the memory test, are nevertheless made possible.

摘要翻译： 集成存储器包含寻址单元，用于基于接收到的寻址信号寻址用于存储器存取的存储器单元。 寻址计算逻辑单元连接到寻址单元。 后者可以由测试模式信号激活，用于存储器的测试操作。 寻址计算逻辑单元接收用于测试操作的命令信号和地址信号，由此计算存储器访问的寻址信号，并将其馈送到寻址单元。 在加载初始参数初始化之后，用于测试操作的命令信号和地址信号被应用于寻址计算逻辑单元，并且读/写操作由访问控制器执行。 在实现的BIST硬件的集成存储器中，在存储器测试期间在其中相对较高的功能和灵活性的情况下仍然是可能的。

公开(公告)号：US20050094461A1

公开(公告)日：2005-05-05

申请号：US10932888

申请日：2004-09-02

申请人： Martin Perner

发明人： Martin Perner

IPC分类号： G11C7/12 ,  G11C7/18 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： An integrated semiconductor memory (1) has a multiplicity of memory cells (Z) and first lines (10) and second lines (20) that can be used to actuate the memory cells (Z). The path of each of the first lines (10) contains a respective device (5) that permits actuation of memory cells exclusively in the region of first subsections (I) of the first lines (10). The devices (5) can be set such that they bring about only partial decoupling of the second subsections (II) of the first lines (10) from the latter s first subsections (I), with memory cells either in the region of the first subsections (I) only or in the region of both subsections (I, II) being able to be actuated, depending on the choice of a relatively short or a relatively long access time to the memory cells. This allows subregions of the semiconductor memory to be used for power-saving and faster memory operation.

摘要翻译： 集成半导体存储器（1）具有可用于致动存储单元（Z）的多个存储单元（Z）和第一行（10）和第二行（20）。 第一行（10）中的每一条的路径包含相应的装置（5），其允许唯一地在第一行（10）的第一子部分（I）的区域中致动存储器单元。 设备（5）可以被设置为使得它们仅使得第一线（10）的第二子部分（II）与后者的第一子部分（I）仅部分去耦，存储器单元在第一 取决于对存储器单元的相对较短或相对长的存取时间的选择，只有部分（I）或两个子部分（I，II）的区域能够被致动。 这允许半导体存储器的子区域用于省电和更快的存储器操作。

公开(公告)号：US06882584B2

公开(公告)日：2005-04-19

申请号：US10317972

申请日：2002-12-12

申请人： Martin Perner

发明人： Martin Perner

IPC分类号： G11C7/10 ,  G11C7/24 ,  G11C8/12 ,  G11C7/00

CPC分类号： G11C7/24 ,  G11C7/1006 ,  G11C7/1048 ,  G11C8/12

摘要： A semiconductor memory and a method for operating the semiconductor memory store information items at least in triplicate at memory addresses in a plurality of memory areas, preferably memory banks, and read the information items therefrom. A checking unit contains synchronization circuits compares the data values that are read and, if the information items that are read differ, can ascertain and possibly immediately correct storage errors. The method of operating the memory enables quasi-random access to memory cells using a permutation circuit. In a test mode for the semiconductor memory, an error log circuit can output error log data instead of or in addition to data values that are read.

摘要翻译： 半导体存储器和用于操作半导体存储器的方法至少在三个存储区中的存储器地址存储至少一式三份的信息项，优选地是存储体，并且从其读取信息项。 检查单元包含同步电路比较读取的数据值，如果读取的信息项不同，则可以确定并且可能立即校正存储错误。 操作存储器的方法使得可以使用置换电路对存储器单元进行准随机存取。 在半导体存储器的测试模式中，错误日志电路可以输出错误日志数据，而不是读取的数据值。

公开(公告)号：US20050028040A1

公开(公告)日：2005-02-03

申请号：US10902160

申请日：2004-07-30

申请人： Martin Perner

发明人： Martin Perner

IPC分类号： G06F11/00 ,  G06F11/22 ,  G06F11/27 ,  G06F11/273 ,  G06F12/00 ,  G11C29/00

CPC分类号： G06F11/2294

摘要： A memory arrangement in a computer system can have at least one memory module with semiconductor components, which are arranged on the memory module, can be operated in parallel and are additionally connected to one another via a serial line. The memory arrangement can have an interface bus for driving the semiconductor components on a module-specific basis, and an interface, which is driven by a memory controller assigned to the memory module via the interface bus and accesses the semiconductor components via the serial line. During normal operation, it is possible to test and adjust the semiconductor components in proximity to the application and on a chip-specific basis via the interface.

摘要翻译： 计算机系统中的存储器装置可以具有至少一个具有半导体部件的存储器模块，其布置在存储器模块上，可以并联操作并且经由串行线路彼此连接。 存储器装置可以具有用于在模块特定的基础上驱动半导体部件的接口总线，以及由经由接口总线分配给存储器模块的存储器控​​制器驱动并经由串行线访问半导体部件的接口。 在正常操作期间，可以通过接口在靠近应用和芯片特定的基础上测试和调整半导体组件。

公开(公告)号：US07778090B2

公开(公告)日：2010-08-17

申请号：US11893415

申请日：2007-08-16

申请人： Martin Perner ,  Nermin Hamzabegovic

发明人： Martin Perner ,  Nermin Hamzabegovic

IPC分类号： G11C7/10

CPC分类号： G11C7/20 ,  G06F11/1028 ,  G11C5/04 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2207/2254

摘要： The invention provides a buffer circuit for a memory module including at least one configuration register bank for storing configuration data of the memory module, an error check logic for performing an error check of input signals applied to the memory module via input pins of the memory module to generate a signature output by the memory module via at least one output pin of the memory module, and a controller which depending on an output request setting stored in a configuration register of the configuration register bank reads out information data the buffer circuit via the output pin of the memory module.

摘要翻译： 本发明提供了一种用于存储器模块的缓冲电路，该存储器模块包括至少一个用于存储存储器模块的配置数据的配置寄存器组，用于通过存储器模块的输入引脚执行施加到存储器模块的输入信号的错误检查的错误校验逻辑 通过存储器模块的至少一个输出引脚来产生由存储器模块输出的签名，并且根据存储在配置寄存器组的配置寄存器中的输出请求设置的控制器经由输出读出缓冲电路的信息数据 引脚的内存模块。

公开(公告)号：US20060152982A1

公开(公告)日：2006-07-13

申请号：US11324801

申请日：2006-01-04

申请人： Martin Perner

发明人： Martin Perner

IPC分类号： G11C7/00

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/12005 ,  G11C2029/1204

摘要： An integrated semiconductor memory device includes sense amplifiers that are connected to in each case one bit line pair via controllable voltage generators. In a test mode state, precharging voltages can be fed to at least one of the bit lines of each one of the bit line pairs via the controllable voltage generators. The level of the precharging voltage is dependent on a data item present at a data terminal. The precharging voltages of a bit line pair can be transferred to an adjacent bit line pair via a coupling unit. In a subsequent evaluation process, the prepared precharging voltages are evaluated by the connected sense amplifier.

摘要翻译： 集成半导体存储器件包括通过可控电压发生器连接到每个情况下的一个位线对的读出放大器。 在测试模式状态下，可以经由可控电压发生器将预充电电压馈送到每一个位线对中的至少一个位线。 预充电电压的电平取决于存在于数据端的数据项。 位线对的预充电电压可以通过耦合单元传送到相邻的位线对。 在随后的评估过程中，所准备的预充电电压由所连接的读出放大器进行评估。