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公开(公告)号：US10186296B2
公开(公告)日：2019-01-22
申请号：US15921610
申请日：2018-03-14
Applicant: Marvell World Trade Ltd.
Inventor： Gregory Burd , Nedeljko Varnica , Heng Tang
Abstract: A method for redundantly storing data includes receiving data at a storage controller, partitioning the data into a plurality of data blocks, generating a first error correction code associated with a first page within the plurality of data blocks, and generating a first redundancy code associated with at least two data blocks within the plurality of data block. The first redundancy code provides additional error recovery if the first error correction code fail. The method further includes storing the plurality of data blocks, the first error correction code, and the first redundancy code across a plurality of solid state storage devices.
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公开(公告)号：US09922678B2
公开(公告)日：2018-03-20
申请号：US14947833
申请日：2015-11-20
Applicant: Marvell World Trade Ltd.
Inventor： Gregory Burd , Nedeljko Varnica , Heng Tang
CPC classification number: G11B20/1833 , G06F11/08 , G06F11/1076 , G11B20/1217 , G11B2020/1222 , G11B2020/1238
Abstract: Systems and techniques include a method including: receiving a data request for first data stored at a storage device; reading second data from discrete units of storage of the storage device, the second data comprising the first data read from two or more of the discrete units of storage, error correction code redundancies read from the two or more of the discrete units of storage, and parity data read from at least one of the discrete units of storage; detecting, based on the error correction code redundancies, an error in a first portion of the first data stored in one of the two or more of the discrete units of storage; and recovering the first portion of the first data using the parity data and a second portion of the first data read from one or more remaining ones of the two or more of the discrete units of storage.
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公开(公告)号：US09323611B2
公开(公告)日：2016-04-26
申请号：US14197426
申请日：2014-03-05
Applicant: Marvell World Trade Ltd.
Inventor： Shashi Kiran Chilappagari , Gregory Burd
CPC classification number: G06F11/1068 , H03M13/1108 , H03M13/1111 , H03M13/1128 , H03M13/3707 , H04L1/0052
Abstract: Systems and methods are provided for decoding data. A first decoder attempts to decode the data based on a hard decision input for a symbol. When the attempt to decode the data based on the hard decision input fails, a request is transmitted reliability information for the symbol. Receiving circuitry receives the reliability information for the symbol, and a second decoder decodes the data based on the reliability information.
Abstract translation: 提供了解码数据的系统和方法。 第一解码器尝试基于用于符号的硬判决输入对数据进行解码。 当基于硬判决输入解码数据的尝试失败时，发送请求被发送用于符号的可靠性信息。 接收电路接收符号的可靠性信息，第二解码器基于可靠性信息对数据进行解码。
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公开(公告)号：US08977813B2
公开(公告)日：2015-03-10
申请号：US14260237
申请日：2014-04-23
Applicant: Marvell World Trade Ltd.
Inventor： Gregory Burd
CPC classification number: G06F11/108 , G06F11/1008 , G06F11/1028 , G06F11/1048 , G06F12/0246 , G06F2212/1032 , G06F2212/7208 , G11C29/52
Abstract: The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a data request for a solid state memory; identifying a logical block grouping corresponding to the data request, wherein the logical block grouping indicates physical data storage blocks spanning at least two distinct memory units of the solid state memory; reading stored data and parity information from at least a portion of the physical data storage blocks spanning the at least two distinct memory units; and recovering data of at least one block of the logical block grouping based on the stored data and the parity information.
Abstract translation: 本公开包括与在固态存储器中实现容错数据存储有关的系统和技术。 在一些实现中，一种方法包括接收对固态存储器的数据请求; 识别对应于所述数据请求的逻辑块分组，其中所述逻辑块分组指示跨越所述固态存储器的至少两个不同存储器单元的物理数据存储块; 从跨越至少两个不同存储器单元的物理数据存储块的至少一部分读取存储的数据和奇偶校验信息; 以及基于所存储的数据和所述奇偶校验信息来恢复所述逻辑块分组的至少一个块的数据。
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5.发明申请SYSTEMS AND METHODS FOR CALIBRATING READ AND WRITE OPERATIONS IN TWO DIMENSIONAL MAGNETIC RECORDING 有权用于在两维磁记录中校准读取和写入操作的系统和方法公开(公告)号：US20150022916A1
公开(公告)日：2015-01-22
申请号：US14331553
申请日：2014-07-15
Applicant: Marvell World Trade Ltd.
Inventor： Qiyue Zou , Michael Madden , Gregory Burd
IPC: G11B5/455
CPC classification number: G11B5/455 , G11B5/012 , G11B5/4886 , G11B5/58 , G11B5/59627 , G11B5/59683 , G11B20/10
Abstract: Systems and methods are provided for calibrating signals retrieved from a storage device using a first reader and a second reader. The systems and methods further include reading a first signal using the first reader and a second signal using the second reader. Control circuitry computes a calibration metric associated with the first reader and the second reader based on the combination of the first signal and the second signal. At least one of the first signal and the second signal is subsequently decoded based in part on the computed calibration metric.
Abstract translation: 提供了用于使用第一读取器和第二读取器校准从存储设备检索的信号的系统和方法。 系统和方法还包括使用第一读取器读取第一信号和使用第二读取器读取第二信号。 控制电路基于第一信号和第二信号的组合来计算与第一读取器和第二读取器相关联的校准度量。 部分地基于所计算的校准度量，随后对第一信号和第二信号中的至少一个进行解码。
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Patent Agency Ranking
公开(公告)号：US20140344647A1
公开(公告)日：2014-11-20
申请号：US14267307
申请日：2014-05-01
Applicant: Marvell World Trade LTD.
Inventor： Shashi Kiran Chilappagari , Gregory Burd
CPC classification number: H03M13/1111 , G06F11/1012 , G06F11/1048 , G06F11/1068 , G11C29/52 , H03M13/1105 , H03M13/1108 , H03M13/2927 , H03M13/2957 , H03M13/2975 , H03M13/3707 , H03M13/3738 , H03M13/3746 , H03M13/3927 , H03M13/41 , H03M13/45 , H03M13/458 , H03M13/6513
Abstract: A controller for a nonvolatile memory device includes a transfer control module and a decoder module. The transfer control module is configured to request a read of data from a flash memory module. The data to be read includes data corresponding to a first codeword. The transfer control module is configured to receive hard decisions corresponding to the first codeword from the flash memory module. The transfer control module is configured to receive soft information corresponding to the first codeword from the flash memory module. Both the hard decisions corresponding to the first codeword and the soft information corresponding to the first codeword are received without receiving any intervening hard decisions or soft information corresponding to another codeword. The decoder module is configured to decode the first codeword using the hard decisions and the soft information corresponding to the first codeword.
Abstract translation: 非易失性存储器件的控制器包括转移控制模块和解码器模块。 转移控制模块被配置为请求从闪存模块读取数据。 要读取的数据包括对应于第一码字的数据。 传送控制模块被配置为从闪存模块接收对应于第一码字的硬判决。 传送控制模块被配置为从闪存模块接收对应于第一码字的软信息。 接收对应于第一码字的硬判决和对应于第一码字的软信息，而不接收与另一码字对应的任何介入的硬判决或软信息。 解码器模块被配置为使用硬判决和对应于第一码字的软信息来解码第一码字。
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公开(公告)号：US20130155776A1
公开(公告)日：2013-06-20
申请号：US13713316
申请日：2012-12-13
Applicant: Marvell World Trade Ltd.
Inventor： Shashi Kiran Chilappagari , Zhengang Chen , Gregory Burd
IPC: G11C16/34
CPC classification number: G11C16/3404 , G11C11/5642 , G11C16/04 , G11C16/26 , G11C16/34 , G11C16/3418 , G11C16/3427
Abstract: A method includes selecting a first memory cell located along a first bit line and a first word line of a memory array. The method further includes selecting a second memory cell located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. A location of the second memory cell is selected based on a predetermined sequence of programming the memory cells. The method further includes writing data in the first memory cell, subsequently writing data in the second memory cell, and reading the first memory cell and the second memory cell. The method further includes detecting one or more states of the second memory causing interference to the first memory cell.
Abstract translation: 一种方法包括选择沿着存储器阵列的第一位线和第一字线定位的第一存储器单元。 该方法还包括选择沿着（i）第一字线，（ii）与第一字线相邻的第二字线，或（iii）与第一字线相邻的第二位线， 线。 基于对存储器单元的预定编程顺序来选择第二存储单元的位置。 该方法还包括在第一存储单元中写入数据，随后在第二存储单元中写入数据，以及读取第一存储单元和第二存储单元。 该方法还包括检测造成对第一存储器单元的干扰的第二存储器的一个或多个状态。
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公开(公告)号：US20180204594A1
公开(公告)日：2018-07-19
申请号：US15921610
申请日：2018-03-14
Applicant: Marvell World Trade Ltd.
Inventor： Gregory Burd , Nedeljko Varnica , Heng Tang
CPC classification number: G11B20/1833 , G06F11/08 , G06F11/1076 , G11B20/1217 , G11B2020/1222 , G11B2020/1238
Abstract: The present disclosure describes systems and techniques relating to storage devices, such as storage devices that employ Shingled Magnetic Recording (SMR). According to an aspect of the described systems and techniques, a device includes: circuitry configured to write stored data and parity data to discrete portions of a Shingled Magnetic Recording (SMR) track in a SMR storage device; and circuitry configured to recover stored data for one of the discrete portions of the SMR track using the parity data and the stored data read from remaining ones of the discrete portions of the SMR track.
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9.发明授权Generating position error signal based on data tracks for rotating magnetic data storage 有权基于用于旋转磁数据存储的数据轨迹生成位置误差信号公开(公告)号：US09384767B2
公开(公告)日：2016-07-05
申请号：US14867302
申请日：2015-09-28
Applicant: Marvell World Trade LTD.
Inventor： Mats Oberg , Gregory Burd
CPC classification number: G11B5/59622 , G11B5/5547 , G11B5/59611 , G11B5/59627 , G11B5/5965 , G11B20/10212 , G11B20/10305
Abstract: A system including an inter-track interference detection module and a position error signal generation module. The inter-track interference detection module determines a first inter-track interference value based on a first signal from a first sensor positioned over a first track of a rotating storage medium. The first inter-track interference value indicates energy contributed by tracks adjacent to the first track compared to energy contributed by the first track. The inter-track interference detection module determines a second inter-track interference value based on a second signal from a second sensor positioned over a second track of the rotating storage medium. The second inter-track interference value indicates energy contributed by tracks adjacent to the second track compared to energy contributed by the second track. The position error signal generation module generates a position error signal based on the first inter-track interference value and the second inter-track interference value.
Abstract translation: 一种包括轨道间干扰检测模块和位置误差信号生成模块的系统。 轨道间干扰检测模块基于位于旋转存储介质的第一轨道上的第一传感器的第一信号来确定第一轨道间干扰值。 第一轨道间干扰值表示与由第一轨道贡献的能量相比，与第一轨道相邻的轨道所贡献的能量。 轨道间干扰检测模块基于位于旋转存储介质的第二轨道上的第二传感器的第二信号来确定第二轨道间干扰值。 第二轨道间干扰值指示与由第二轨道贡献的能量相比较的与第二轨道相邻的轨道所贡献的能量。 位置误差信号产生模块基于第一轨道间干扰值和第二轨道间干扰值产生位置误差信号。
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10.发明授权公开(公告)号：US09311937B2
公开(公告)日：2016-04-12
申请号：US14331553
申请日：2014-07-15
Applicant: Marvell World Trade Ltd.
Inventor： Qiyue Zou , Michael Madden , Gregory Burd
CPC classification number: G11B5/455 , G11B5/012 , G11B5/4886 , G11B5/58 , G11B5/59627 , G11B5/59683 , G11B20/10
Abstract: Systems and methods are provided for calibrating signals retrieved from a storage device using a first reader and a second reader. The systems and methods further include reading a first signal using the first reader and a second signal using the second reader. Control circuitry computes a calibration metric associated with the first reader and the second reader based on the combination of the first signal and the second signal. At least one of the first signal and the second signal is subsequently decoded based in part on the computed calibration metric.
Abstract translation: 提供了用于使用第一读取器和第二读取器校准从存储设备检索的信号的系统和方法。 系统和方法还包括使用第一读取器读取第一信号和使用第二读取器读取第二信号。 控制电路基于第一信号和第二信号的组合来计算与第一读取器和第二读取器相关联的校准度量。 部分地基于所计算的校准度量，随后对第一信号和第二信号中的至少一个进行解码。
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