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公开(公告)号：US20110221516A1
公开(公告)日：2011-09-15
申请号：US12987112
申请日：2011-01-08
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , H03K19/0016
摘要： Information technology equipment includes a circuit block, a local power source line for supplying a power source to the circuit block, a power source line, and a first transistor which is provided with a source-drain path thereof between the power source line and the local power source line, in which the first transistor is controlled to an OFF state in a first state, and is controlled to an ON state in a second state, and when the first state is shifted to the second state, the first transistor is controlled such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a predetermined value.
摘要翻译： 信息技术设备包括电路块，用于向电路块提供电源的局部电源线，电源线和在电源线和本地电源线之间设置有源极 - 漏极路径的第一晶体管 电源线，其中第一晶体管在第一状态下被控制为OFF状态，并且在第二状态下被控制为ON状态，并且当第一状态转移到第二状态时，第一晶体管被控制为 改变在第一晶体管的源极 - 漏极路径中流动的电流的速率不超过预定值。
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公开(公告)号：US20100264735A1
公开(公告)日：2010-10-21
申请号：US12759520
申请日：2010-04-13
IPC分类号： H02J1/10
CPC分类号： G06F1/32 , G06F1/3287 , Y02D10/171 , Y10T307/50
摘要： Objects of the invention are to minimize power consumption while maintaining the required information processing capabilities of an LSI chip by supplying multiple voltages to the LSI chip such that its circuit blocks receive necessary voltages and to prevent an increase in the chip area of the LSI chip and performance degradation of signal wires, which may result from the supply of the multiple voltages, by reducing the number of power supply wires.In an LSI chip to which two voltages are supplied, high voltage wires are more densely spaced than low voltage wires. By selectively applying voltages based on circuit block performance, it is possible to reduce power consumption while maintaining the amount of information processed by the LSI chip.
摘要翻译： 本发明的目的是通过向LSI芯片提供多个电压使得其电路块接收必要的电压并防止LSI芯片的芯片面积的增加来保持LSI芯片所需的信息处理能力，从而最小化功耗，并且 通过减少电源线的数量，可能由多个电压的供给引起的信号线的性能下降。 在提供两个电压的LSI芯片中，高压电线与低压电线相比密度更高。 通过基于电路块性能选择性地施加电压，可以在保持由LSI芯片处理的信息量的同时降低功耗。
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公开(公告)号：US20080144365A1
公开(公告)日：2008-06-19
申请号：US11943495
申请日：2007-11-20
IPC分类号： G11C11/34
CPC分类号： G11C11/417
摘要： In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.
摘要翻译： 在本发明中，实现了高制造成品率，并补偿了CMOS.SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。
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公开(公告)号：US20120195110A1
公开(公告)日：2012-08-02
申请号：US13443511
申请日：2012-04-10
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。
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公开(公告)号：US20120120738A1
公开(公告)日：2012-05-17
申请号：US13353949
申请日：2012-01-19
申请人： Masanao YAMAOKA , Kenichi OSADA
发明人： Masanao YAMAOKA , Kenichi OSADA
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/412
摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.
摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。
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公开(公告)号：US20110133786A1
公开(公告)日：2011-06-09
申请号：US13028212
申请日：2011-02-15
申请人： Masanao YAMAOKA , Kenichi OSADA
发明人： Masanao YAMAOKA , Kenichi OSADA
IPC分类号： H03K5/00
CPC分类号： H03K19/00346
摘要： A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.
摘要翻译： 可以在第一逻辑电路和第二逻辑电路之间提供可执行速度性能测量的速度性能测量电路。 速度性能测量电路包括存储第一数据的第一触发器，延迟第一数据并产生第二数据的第一延迟电路和存储第二数据的第二触发器。 此外，速度性能测量电路包括第一比较器电路，其将第一触发器的输出与第二触发器的输出进行比较;以及第三触发器，其根据第一时钟的定时存储来自第一比较器电路的输出数据 信号。 将正常路径中的数据与延迟一定时间的路径中的数据进行比较以测量速度，并且基于这样的比较确定电路的功率电压。 因此，可以测量关键路径中的功率电压的速度变化。
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公开(公告)号：US20120147662A1
公开(公告)日：2012-06-14
申请号：US13350340
申请日：2012-01-13
IPC分类号： G11C11/40
CPC分类号： G11C11/417
摘要： High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.
摘要翻译： 实现了高制造成品率，补偿了CMOS·SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据确定结果被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS·SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置电压施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。
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公开(公告)号：US20100054049A1
公开(公告)日：2010-03-04
申请号：US12543499
申请日：2009-08-18
申请人： Masanao YAMAOKA , Kenichi OSADA
发明人： Masanao YAMAOKA , Kenichi OSADA
CPC分类号： G11C8/08 , G11C11/412
摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.
摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。
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公开(公告)号：US20110102019A1
公开(公告)日：2011-05-05
申请号：US12987664
申请日：2011-01-10
IPC分类号： H01L25/00 , H01L27/092 , H01L29/772
CPC分类号： H01L29/78648 , G11C11/412 , H01L21/823878 , H01L21/84 , H01L27/0928 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/4908 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.
摘要翻译： 完全耗尽型SOI衬底的MISFETS的阈值不能通过改变杂质密度来控制，就像体硅硅MISFET那样。 因此，难以为每个电路设定合适的阈值。 根据本发明的半导体器件，构成存储单元的P沟道型MISFET的栅电极由N型多晶硅制成，N沟道型MISFET的栅电极由P型多晶硅制成，栅电极为P 通道型和外围电路的N沟道型MISFET和逻辑电路由P型硅锗制成。 对于使用SOI衬底的每个电路，可以实现合适的阈值，从而可以充分利用SOI衬底的特性。
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公开(公告)号：US20090153182A1
公开(公告)日：2009-06-18
申请号：US12335331
申请日：2008-12-15
申请人： Masanao YAMAOKA , Kenichi Osada
发明人： Masanao YAMAOKA , Kenichi Osada
IPC分类号： H03K19/00
CPC分类号： H03K19/00346
摘要： A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.
摘要翻译： 可以在第一逻辑电路和第二逻辑电路之间提供可执行速度性能测量的速度性能测量电路。 速度性能测量电路包括存储第一数据的第一触发器，延迟第一数据并产生第二数据的第一延迟电路和存储第二数据的第二触发器。 此外，速度性能测量电路包括第一比较器电路，其将第一触发器的输出与第二触发器的输出进行比较;以及第三触发器，其根据第一时钟的定时存储来自第一比较器电路的输出数据 信号。 将正常路径中的数据与延迟一定时间的路径中的数据进行比较以测量速度，并且基于这样的比较确定电路的功率电压。 因此，可以测量关键路径中的功率电压的速度变化。
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