公开(公告)号：US07254069B2

公开(公告)日：2007-08-07

申请号：US10372284

申请日：2003-02-25

申请人： Masaru Haraguchi ,  Takeshi Fujino

发明人： Masaru Haraguchi ,  Takeshi Fujino

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C29/785 ,  G11C29/848

摘要： Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to respective memory cell array blocks. The storage data of the column redundancy data storage circuits is transferred to redundancy data hold circuits arranged in spare column decoder bands adjacent to the data paths for transferring internal data, and are decoded for selection of a page in the spare decoder bands during column access. Therefore, it is possible to reduce the occupation area of a fuse program circuit which programs redundancy data for repairing a defective column.

摘要翻译： 存储用于修复有缺陷的列的列冗余数据的列冗余数据存储电路块被布置成对应于各个存储单元阵列块。 列冗余数据存储电路的存储数据被传送到与用于传送内部数据的数据路径相邻的备用列解码器带中的冗余数据保持电路，并且在列访问期间被解码用于在备用解码器频带中选择页面。 因此，可以减少用于修复缺陷列的冗余数据的保险丝编程电路的占用面积。

公开(公告)号：US07433251B2

公开(公告)日：2008-10-07

申请号：US11765551

申请日：2007-06-20

申请人： Masaru Haraguchi ,  Takeshi Fujino

发明人： Masaru Haraguchi ,  Takeshi Fujino

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C29/785 ,  G11C29/848

摘要： Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to memory cell array blocks, respectively. The storage data of the column redundancy data storage circuits is transferred to redundancy data hold circuits arranged in spare column decoder bands adjacent to the data paths for transferring internal data, and are decoded for selection of a page in the spare decoder bands in column access. Therefore, it is possible to reduce the occupation area of a fuse program circuit which programs redundancy data for repairing a defective column.

摘要翻译： 存储用于修复缺陷列的列冗余数据的列冗余数据存储电路块分别对应于存储单元阵列块布置。 列冗余数据存储电路的存储数据被传送到与用于传送内部数据的数据路径相邻的备用列解码器带中的冗余数据保持电路，并且被解码用于在列访问中的备用解码器频带中的页面选择。 因此，可以减少用于修复缺陷列的冗余数据的保险丝编程电路的占用面积。

公开(公告)号：US06643214B2

公开(公告)日：2003-11-04

申请号：US10166122

申请日：2002-06-11

申请人： Yasuhiko Taito ,  Takeshi Fujino ,  Masaru Haraguchi

发明人： Yasuhiko Taito ,  Takeshi Fujino ,  Masaru Haraguchi

IPC分类号： G11C800

CPC分类号： G11C7/1096 ,  G11C7/1048 ,  G11C7/1078 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/229

摘要： This DRAM includes a driver circuit which is provided to be common to a plurality of columns and which lowers level of one of selected first and second bit lines to “L” level in accordance with potentials of first and second write data lines. Therefore, as compared with a conventional DRAM in which a driver circuit is provided for each column, the number of transistors is decreased and a layout area is reduced.

公开(公告)号：US20070242506A1

公开(公告)日：2007-10-18

申请号：US11765551

申请日：2007-06-20

申请人： Masaru Haraguchi ,  Takeshi Fujino

发明人： Masaru Haraguchi ,  Takeshi Fujino

IPC分类号： G11C11/34

CPC分类号： G11C29/80 ,  G11C29/785 ,  G11C29/848

摘要： Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to memory cell array blocks, respectively. The storage data of the column redundancy data storage circuits is transferred to redundancy data hold circuits arranged in spare column decoder bands adjacent to the data paths for transferring internal data, and are decoded for selection of a page in the spare decoder bands in column access. Therefore, it is possible to reduce the occupation area of a fuse program circuit which programs redundancy data for repairing a defective column.

摘要翻译： 存储用于修复缺陷列的列冗余数据的列冗余数据存储电路块分别对应于存储单元阵列块布置。 列冗余数据存储电路的存储数据被传送到与用于传送内部数据的数据路径相邻的备用列解码器带中的冗余数据保持电路，并且被解码用于在列访问中的备用解码器频带中的页面选择。 因此，可以减少用于修复缺陷列的冗余数据的保险丝编程电路的占用面积。

公开(公告)号：US20080181047A1

公开(公告)日：2008-07-31

申请号：US12010674

申请日：2008-01-29

申请人： Masaru Haraguchi ,  Tokuya Osawa

发明人： Masaru Haraguchi ,  Tokuya Osawa

IPC分类号： G11C8/18

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/023

摘要： A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.

摘要翻译： 本发明的半导体器件包括确定相移量的DLL电路，在测试模式时将相移量移位预定相位的运算电路，设定相移量的寄存器以及移相量的发送电路 一个阶段到设定阶段发送或接收一个信号。 传输电路具有第一移相器，其将第一信号移位到设定相位，第一双向缓冲器，以测试模式时间回送第一信号;第二移相器，其将从第一双向缓冲器输出的信号相移 第三移相器，其将第三信号相移，在测试模式时间使第三信号回路的第二双向缓冲器，使从第二双向缓冲器输出的信号相移的第四移相器;以及FIFO， 取出第二移相器或第四移相器的输出信号。

公开(公告)号：US06781903B2

公开(公告)日：2004-08-24

申请号：US10409593

申请日：2003-04-09

申请人： Atsuo Mangyo ,  Masaru Haraguchi ,  Akira Yamazaki

发明人： Atsuo Mangyo ,  Masaru Haraguchi ,  Akira Yamazaki

IPC分类号： G11C700

CPC分类号： G11C11/40611 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/406 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A semiconductor memory device includes a first data line electrically connected to selected one of a plurality of memory cells in response to activation of a word line, a second data line provided hierarchically with respect to the first data line, a read circuit provided between the first data line and the second data line to drive the second data line to a fixed voltage with a driving power according to a voltage on the first data line at the time of data reading, and a voltage supply control circuit for supplying a predetermined voltage to the second data line in response to a precharge/equalize instruction. The voltage supply control circuit includes a voltage supply stop circuit disconnecting the second data line from the predetermined voltage in a predetermined period except for the time of data reading.

公开(公告)号：US06449198B1

公开(公告)日：2002-09-10

申请号：US09717375

申请日：2000-11-22

申请人： Kei Hamade ,  Takeshi Hamamoto ,  Masaru Haraguchi ,  Yasuhiro Konishi

发明人： Kei Hamade ,  Takeshi Hamamoto ,  Masaru Haraguchi ,  Yasuhiro Konishi

IPC分类号： G11C700

CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C11/4097

摘要： In the SDRAM, a selector selects one of four global IO line pairs according to a column block select signal and a word configuration selecting signal, and connects the selected global IO line pair to an input/output node pair of a preamplifier in a pulsed manner for a prescribed period of time. Since the equalization of the global IO line pair can be started immediately after the global IO line pair is connected in a pulsed manner to the input/output node pair of the preamplifier, longer equalization period for the global IO line can be set aside so that the read operation can be stabilized.

摘要翻译： 在SDRAM中，选择器根据列块选择信号和字配置选择信号来选择四个全局IO线对中的一个，并将所选择的全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对 在规定的时间内。 由于全局IO线对的均衡可以在全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对之后立即开始，所以可以将全局IO线的更长的均衡周期放在一边，以便 读取操作可以稳定。

公开(公告)号：US07983112B2

公开(公告)日：2011-07-19

申请号：US12010674

申请日：2008-01-29

申请人： Masaru Haraguchi ,  Tokuya Osawa

发明人： Masaru Haraguchi ,  Tokuya Osawa

IPC分类号： G11C8/16

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/023

摘要： A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.

摘要翻译： 本发明的半导体器件包括确定相移量的DLL电路，在测试模式时将相移量移位预定相位的运算电路，设定相移量的寄存器以及移相量的发送电路 一个阶段到设定阶段发送或接收一个信号。 传输电路具有第一移相器，其将第一信号移位到设定相位，第一双向缓冲器，以测试模式时间回送第一信号;第二移相器，其将从第一双向缓冲器输出的信号相移 第三移相器，其将第三信号相移，在测试模式时间使第三信号回路的第二双向缓冲器，使从第二双向缓冲器输出的信号相移的第四移相器;以及FIFO， 取出第二移相器或第四移相器的输出信号。

公开(公告)号：US20100257324A1

公开(公告)日：2010-10-07

申请号：US12751810

申请日：2010-03-31

申请人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

发明人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

IPC分类号： G06F12/00

CPC分类号： G11C8/08 ,  G11C7/1066

摘要： A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.

摘要翻译： 可变延迟线接收并延迟从数据源侧与传送数据同步预定周期的数据选通信号，并将延迟数据选通信号和非延迟数据选通信号提供给检测器。 当非延迟数据选通信号从L电平上升到H电平时，当延迟的数据选通信号为L电平时，检测器确定前导码周期结束并传送有效数据。 根据检测结果，接口电路单元接收传送数据并初始化接收地址。 当后同步码结束时，数据选通信号变为高阻态。 数据选通信号的变化可以避免毛刺噪声的影响，可以快速准确地执行数据传送。

公开(公告)号：US20080068040A1

公开(公告)日：2008-03-20

申请号：US11852032

申请日：2007-09-07

申请人： Chikayoshi Morishima ,  Tokuya Osawa ,  Masaru Haraguchi ,  Yoshihiro Yamashita

发明人： Chikayoshi Morishima ,  Tokuya Osawa ,  Masaru Haraguchi ,  Yoshihiro Yamashita

IPC分类号： H03K19/0175

CPC分类号： H03K19/0005 ,  H03K19/018578

摘要： There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.

摘要翻译： 提供了一种包括输出缓冲电路的半导体器件，其减少用于阻抗调整的电路占据的面积，并允许高速阻抗调节。 在阻抗测量电路中，测量与构成输出缓冲电路的多个晶体管尺寸相同尺寸的参考晶体管的尺寸相等的阻抗值。 基于来自阻抗测量电路的测量结果，阻抗代码产生电路将对应于基准晶体管的阻抗值的阻抗代码输出到输出缓冲器代码产生电路。 输出缓冲器代码产生电路通过执行算术运算处理产生用于调节输出缓冲器电路的阻抗的输出缓冲器代码，以提供基于阻抗代码的物镜阻抗。