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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06449198B1

    公开(公告)日：2002-09-10

    申请号：US09717375

    申请日：2000-11-22

    申请人： Kei Hamade ,  Takeshi Hamamoto ,  Masaru Haraguchi ,  Yasuhiro Konishi

    发明人： Kei Hamade ,  Takeshi Hamamoto ,  Masaru Haraguchi ,  Yasuhiro Konishi

    IPC分类号： G11C700

    CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C11/4097

    摘要： In the SDRAM, a selector selects one of four global IO line pairs according to a column block select signal and a word configuration selecting signal, and connects the selected global IO line pair to an input/output node pair of a preamplifier in a pulsed manner for a prescribed period of time. Since the equalization of the global IO line pair can be started immediately after the global IO line pair is connected in a pulsed manner to the input/output node pair of the preamplifier, longer equalization period for the global IO line can be set aside so that the read operation can be stabilized.

    摘要翻译： 在SDRAM中，选择器根据列块选择信号和字配置选择信号来选择四个全局IO线对中的一个，并将所选择的全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对 在规定的时间内。 由于全局IO线对的均衡可以在全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对之后立即开始，所以可以将全局IO线的更长的均衡周期放在一边，以便 读取操作可以稳定。

    Semiconductor memory device having hierarchical word line structure
    2.
    发明授权
    Semiconductor memory device having hierarchical word line structure 失效
    具有分层字线结构的半导体存储器件

    公开(公告)号：US6157588A

    公开(公告)日：2000-12-05

    申请号：US229343

    申请日：1999-01-13

    申请人： Yasuhiro Matsumoto ,  Mikio Asakura ,  Takeshi Hamamoto ,  Kei Hamade

    发明人： Yasuhiro Matsumoto ,  Mikio Asakura ,  Takeshi Hamamoto ,  Kei Hamade

    IPC分类号： G11C11/407 ,  G11C7/18 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/02

    CPC分类号： G11C7/18 ,  G11C11/4097

    摘要： First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.

    摘要翻译： 第一和第二全局输入/输出线在第一和第二主块之间扭转。 第一主块中的第一和第二SD信号线分别布置成与第一和第二全局输入/输出线相邻。 第二主块中的第一和第二SD信号线分别布置成与第二和第一全局输入/输出线相邻。 为第一或第二SD信号线提供的SD信号对第一和第二全局输入/输出线施加相同的噪声，使得在第一和第二全局输入/输出线之间基本上消除了噪声的影响。 因此，全球输入/输出线路具有更高的抗噪声能力，而不会增加布局面积。

    Buffer circuit of a semiconductor memory device
    3.
    发明授权
    Buffer circuit of a semiconductor memory device 失效
    半导体存储器件的缓冲电路

    公开(公告)号：US5469402A

    公开(公告)日：1995-11-21

    申请号：US305632

    申请日：1994-09-14

    申请人： Tadaaki Yamauchi ,  Kei Hamade ,  Yoshikazu Morooka

    发明人： Tadaaki Yamauchi ,  Kei Hamade ,  Yoshikazu Morooka

    IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C8/18 ,  G11C11/408

    CPC分类号： G11C8/06 ,  G11C8/18

    摘要： An internal address signal is outputted quickly by connecting nMOS transistors in series to inverters forming a latching circuit of a row address buffer circuit, applying an external row address signal to the gate of a nMOS transistor, applying a delayed activation signal .phi.2 to the gate of the nMOS transistors, grounding the gate of the nMOS transistor, triggering nMOS transistors into complete conduction by the delayed activation signal .phi.2 to reduce the ON resistance. A column address buffer circuit receives a ZCAS circuit by an NOR gate, and an external column address signal by an NAND gate during standby, to prevent a flow of a through current.

    摘要翻译： 通过将nMOS晶体管串联连接到形成行地址缓冲电路的锁存电路的反相器，快速地输出内部地址信号，向nMOS晶体管的栅极施加外部行地址信号，将延迟的激活信号phi2施加到栅极 nMOS晶体管的栅极接地，将nMOS晶体管触发通过延迟的激活信号phi2完全导通，以降低导通电阻。 列地址缓冲电路通过NOR门接收ZCAS电路，在待机期间通过NAND门接收外部列地址信号，以防止通过电流的流动。

    Test circuit for a semiconductor memory device and method for burn-in test
    7.
    发明授权
    Test circuit for a semiconductor memory device and method for burn-in test 有权
    一种用于半导体存储器件的测试电路和用于老化测试的方法

    公开(公告)号：US6055199A

    公开(公告)日：2000-04-25

    申请号：US176880

    申请日：1998-10-21

    申请人： Kei Hamade ,  Kiyohiro Furutani ,  Takashi Kono ,  Mikio Asakura

    发明人： Kei Hamade ,  Kiyohiro Furutani ,  Takashi Kono ,  Mikio Asakura

    IPC分类号： G11C29/50 ,  G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/401

    摘要： A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.

    摘要翻译： 用于向具有分别连接到字线和位线的多个存储单元的半导体存储器件的存储单元提供应力的电路包括用于产生位线的预充电电压的电路，位线预充电和均衡电路， 连接在所述用于产生位线的预充电电压的电路和所述存储单元之间，连接到位线预充电和均衡电路的焊盘，用于通过相应的位线向所述存储器单元施加期望的电压，以及连接到电路的电路 用于产生用于产生用于产生用于产生用于产生位线的预充电电压的所述电路的操作的信号的位线的预充电电压，从而可以容易地实现电池检查器图案，以便不仅在栅极氧化膜中屏蔽可能的故障， 电容器电介质，存储节点结等，从外部施加任意的应力电压 设备侧。

    Semiconductor memory device having improved hierarchical I/O line pair structure
    8.
    发明授权
    Semiconductor memory device having improved hierarchical I/O line pair structure 失效
    具有改进的分级I / O线对结构的半导体存储器件

    公开(公告)号：US5650975A

    公开(公告)日：1997-07-22

    申请号：US710109

    申请日：1996-09-12

    申请人： Kei Hamade ,  Kenichi Yasuda ,  Mikio Asakura ,  Hideto Hidaka

    发明人： Kei Hamade ,  Kenichi Yasuda ,  Mikio Asakura ,  Hideto Hidaka

    IPC分类号： G11C11/401 ,  G11C7/10 ,  H01L21/8242 ,  H01L27/108 ,  G11C13/00

    CPC分类号： G11C7/10 ,  G11C7/1048

    摘要： In a memory plane of a semiconductor memory device, transmission gate circuits for transferring data between local I/O line pair and global I/O line pair, and equalizing circuits for equalizing the local I/O line pair are arranged alternately on both sides of a shunt region. All the global I/O line pairs extend entirely over the memory plane. One and the other global I/O lines are arranged in symmetry, with a line for transmitting bit line precharge voltage, cell plate voltage or local input/output line equalizing signal being the center.

    摘要翻译： 在半导体存储器件的存储器平面中，用于在本地I / O线对和全局I / O线对之间传输数据的传输门电路以及用于均衡本地I / O线对的均衡电路交替布置在 一个分流区域。 所有全局I / O线对完全延伸到存储器平面上。 一个和另一个全局I / O线对称布置，用于传输位线预充电电压，单元板电压或本地输入/输出线均衡信号为中心的线。

    Semiconductor memory device having multi-bit testing function
    9.
    发明授权
    Semiconductor memory device having multi-bit testing function 失效
    具有多位测试功能的半导体存储器件

    公开(公告)号：US06816422B2

    公开(公告)日：2004-11-09

    申请号：US10291776

    申请日：2002-11-12

    申请人： Kei Hamade ,  Takashi Kono ,  Kiyohiro Furutani

    发明人： Kei Hamade ,  Takashi Kono ,  Kiyohiro Furutani

    IPC分类号： G11C700

    CPC分类号： G11C29/40 ,  G11C29/34 ,  G11C2029/0405 ,  G11C2029/2602

    摘要： In a multi-bit test, an I/O combiner degenerates data of a plurality of bits read from a memory cell array to first to fourth data bus pairs in parallel and outputs the degenerated data to a fifth data bus. A read amplifier compares a logic level of the degenerated data received from the I/O combiner with a logic level of expected value data. If the logic level of the degenerated data coincides with the logic level of the expected value data, the read amplifier determines that data write and read to and from the plurality of bits have been normally performed. As a result, a semiconductor memory device can detect a word line defect in the multi-bit test.

    摘要翻译： 在多位测试中，I / O组合器并行地将从存储单元阵列读取的多个位的数据退格为第一至第四数据总线对，并将退化的数据输出到第五数据总线。 读取放大器将从I / O组合器接收的退化数据的逻辑电平与期望值数据的逻辑电平进行比较。 如果退化数据的逻辑电平与期望值数据的逻辑电平一致，则读取放大器确定对多个位的数据写入和读取已经被正常地执行。 结果，半导体存储器件可以检测多位测试中的字线缺陷。

    Semiconductor device operable in a plurality of test operation modes
    10.
    发明授权
    Semiconductor device operable in a plurality of test operation modes 失效
    可在多个测试操作模式中操作的半导体器件

    公开(公告)号：US06333879B1

    公开(公告)日：2001-12-25

    申请号：US09226155

    申请日：1999-01-07

    申请人： Tetsuo Kato ,  Kei Hamade

    发明人： Tetsuo Kato ,  Kei Hamade

    IPC分类号： G11C700

    CPC分类号： G11C29/028 ,  G11C29/02 ,  G11C29/12 ,  G11C29/46 ,  G11C29/50 ,  G11C2029/5004

    摘要： A circuit generating a test mode instructing signal includes a test mode register circuit which is set to a state disabling instruction of a test mode in a standby state. An intended test mode can be accurately selected even when the test mode is instructed in accordance with a plurality of external signals varied in timing from each other. A semiconductor device allows accurate and efficient execution of the test without requiring increase in area occupied by an array.

    摘要翻译： 产生测试模式指示信号的电路包括被设置为处于待机状态的测试模式的状态禁用指令的测试模式寄存器电路。 即使当根据在彼此定时变化的多个外部信号来指示测试模式时，也可以准确地选择预期的测试模式。 半导体器件允许准确而有效地执行测试，而不需要增加阵列占用的面积。