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1.发明授权Interface circuit coupling semiconductor test apparatus with tested semiconductor device 有权接口电路耦合半导体测试设备与测试的半导体器件公开(公告)号：US06954079B2
公开(公告)日：2005-10-11
申请号：US10462743
申请日：2003-06-17
IPC分类号： G01R31/28 , G01R31/319 , H03K19/0175 , G01R31/26
CPC分类号： G01R31/31926 , G01R31/31924
摘要： The interface circuit includes n buffer circuits, switches for connecting an external pin of a tester to input nodes of n buffer circuits and connecting output nodes of n buffers respectively to n DUTs when a signal is provided from the tester to n DUTs, and successively connecting n DUTs to the external pin of the tester by a prescribed time period when voltage-ampere characteristics of n DUTs are measured. Therefore the number of devices that can be measured by the tester at a time can be increased by n times. As a result, the test cost can be reduced and the test accuracy can be improved.
摘要翻译： 接口电路包括n个缓冲电路，用于将测试器的外部引脚连接到n个缓冲电路的输入节点并将n个缓冲器的输出节点分别连接到n个DUT的开关，当从测试仪提供信号到n个DUT时，连续连接 n测量n个DUT的电压安培特性时，将DUT连接到测试仪的外部引脚。 因此，一次可以由测试仪测量的设备的数量可以增加n倍。 结果，可以降低测试成本并且可以提高测试精度。
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2.发明授权公开(公告)号：US06281698B1
公开(公告)日：2001-08-28
申请号：US09467153
申请日：1999-12-20
IPC分类号： G01R3126
CPC分类号： G01R31/3191
摘要： A waveform and timing generation circuit 28, a skew circuit 30, and a pin driver 32 are provided for each of a plurality of I/O terminals 22 corresponding respectively to a plurality of pins furnished on an LSI. A relay 44 and a loop control circuit 46 are provided to feed an output signal of the pin driver 32 back to an input side of the waveform and timing generation circuit 28. A skew board 100 is used to adjust the skew circuit 30, whereby the initial timing calibration is carried out. With the skew circuit 30 thus adjusted, oscillations are generated over the feedback path, and the number of resulting pulses is counted (to obtain pulse cycles). When the skew circuit 30 is adjusted so that the pulse count above matches the number of pulses generated during oscillations, a simplified form of timing calibration is implemented.
摘要翻译： 为分别对应于LSI上提供的多个引脚的多个I / O端子22中的每一个提供波形和定时产生电路28，偏斜电路30和引脚驱动器32。 设置有继电器44和回路控制电路46，以将引脚驱动器32的输出信号反馈回波形的输入侧和定时产生电路28.偏斜板100用于调整偏斜电路30，由此， 执行初始定时校准。 通过这样调整偏斜电路30，在反馈路径上产生振荡，并且对所得到的脉冲的数量进行计数（以获得脉冲周期）。 当偏斜电路30被调整为使得上面的脉冲数与在振荡期间产生的脉冲数相匹配时，实现了简化形式的定时校准。
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公开(公告)号：US07079060B2
公开(公告)日：2006-07-18
申请号：US11048723
申请日：2005-02-03
IPC分类号： H03M1/12
CPC分类号： G01R31/31924 , G01R19/257 , G01R29/0276
摘要： In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.
摘要翻译： 在测试电路中，确定电路进行功能测试，以确定测量目标器件的模拟信号ANS的波形的斜率部分的定时是否在规格范围内。 只有当模拟信号ANS的电位在参考电位VOL，VOH之间的范围内时，ADC才执行AD转换。 分析单元从ADC分析数字数据，并进行倾斜波形测试，以评估模拟信号ANS波形的倾斜状态。 因此，可以在不需要大容量存储电路的情况下，在任意电压幅度的范围内，以任意数量的区间划分的装置的模拟信号ANS的波形的斜率部分进行AD转换。 可以并行地执行由判定电路进行的功能测试和分析单元的倾斜波形测试。
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公开(公告)号：US20050179576A1
公开(公告)日：2005-08-18
申请号：US11048723
申请日：2005-02-03
IPC分类号： G01R31/28 , G01R19/257 , G01R29/027 , G01R31/319 , H03M1/06
CPC分类号： G01R31/31924 , G01R19/257 , G01R29/0276
摘要： In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.
摘要翻译： 在测试电路中，确定电路进行功能测试，以确定测量目标器件的模拟信号ANS的波形的斜率部分的定时是否在规格范围内。 只有当模拟信号ANS的电位在参考电位VOL，VOH之间的范围内时，ADC才执行AD转换。 分析单元从ADC分析数字数据，并进行倾斜波形测试，以评估模拟信号ANS波形的倾斜状态。 因此，可以在不需要大容量存储电路的情况下，在任意电压幅度的范围内，以任意数量的区间划分的装置的模拟信号ANS的波形的斜率部分进行AD转换。 可以并行地执行由判定电路进行的功能测试和分析单元的倾斜波形测试。
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公开(公告)号：US06546525B2
公开(公告)日：2003-04-08
申请号：US09761179
申请日：2001-01-18
IPC分类号： G06F1750
CPC分类号： G01R31/31908 , G01R31/31922
摘要： An LSI testing apparatus of the invention comprises: a plurality of pins P1, P2, . . . PN; function units 10, 11 and 12 which supply the pins with LSI testing signals, which have functions for making judgments on tests, and which are furnished for each of the pins; and clock mask function units 15A and 15B furnished on the input side of each function unit. Upon testing, any unused pin and function are detected so as to mask the clock mask function unit corresponding to the detected pin and function, whereby power dissipation is reduced in terms of unused pins and functions.
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6.发明授权Jitter measurement circuit for measuring jitter of measurement target signal on the basis of sampling data string obtained by using ideal cyclic signal 失效基于通过使用理想循环信号获得的采样数据串测量测量目标信号抖动的抖动测量电路公开(公告)号：US06934648B2
公开(公告)日：2005-08-23
申请号：US10364500
申请日：2003-02-12
申请人： Hisayoshi Hanai , Teruhiko Funakura , Hisaya Mori
发明人： Hisayoshi Hanai , Teruhiko Funakura , Hisaya Mori
CPC分类号： G01R29/26
摘要： A jitter measurement circuit includes: a conversion section sampling one of a reference signal and a measurement target signal in response to the other of the signals, thereby obtaining a sampling data string; and a determination section measuring jitter of the measurement target signal on the basis of the sampling data string obtained by the conversion section. Since the reference signal is a stable signal having a predetermined cycle, the sampling data string as a measurement result depends on the measurement target signal. Therefore, it is possible to simply measure jitter level in accordance with irregularity of the measurement result and on the basis of relative measurement to expected value data.
摘要翻译： 抖动测量电路包括：响应于另一个信号对参考信号和测量目标信号之一进行采样的转换部分，从而获得采样数据串; 以及确定部，其基于由转换部获得的采样数据串来测量测量目标信号的抖动。 由于参考信号是具有预定周期的稳定信号，作为测量结果的采样数据串取决于测量目标信号。 因此，可以根据测量结果的不规则性和基于对期望值数据的相对测量来简单地测量抖动水平。
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公开(公告)号：US06651023B2
公开(公告)日：2003-11-18
申请号：US09927367
申请日：2001-08-13
申请人： Hisaya Mori , Shinji Yamada , Teruhiko Funakura
发明人： Hisaya Mori , Shinji Yamada , Teruhiko Funakura
IPC分类号： G06F1300
CPC分类号： G01R31/31919 , G01R31/3167 , G01R31/31935
摘要： A semiconductor test apparatus includes an analog-to-digital converter for converting into a digital signal an analog output from a circuit under test; a test-apparatus-ADC-control-signal generation circuit for generating a control signal for the analog-to-digital converter in accordance with an activation signal entered from the outside; a measured data memory for storing, as measured data for each conversion, a signal output from the analog-to-digital converter; an address counter for generating an address signal for the measured data memory; a DAC counter for generating data to be input to the circuit under test; and a data write control circuit which produces, in response to a flag signal output from the analog-to-digital converter and representing that conversion is being performed, an update signal for the address counter, a memory write signal for the measured data memory, and an update signal for the DAC counter.
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8.发明授权Threshold analysis system capable of deciding all threshold voltages included in memory device through single processing 有权阈值分析系统能够通过单一处理来决定存储器件中包括的所有阈值电压公开(公告)号：US06634004B1
公开(公告)日：2003-10-14
申请号：US09706696
申请日：2000-11-07
申请人： Shinji Yamada , Hisaya Mori , Teruhiko Funakura
发明人： Shinji Yamada , Hisaya Mori , Teruhiko Funakura
IPC分类号： G11C2900
CPC分类号： G11C29/50004 , G11C16/04 , G11C16/34 , G11C29/50 , G11C2029/5604 , G11C2029/5606
摘要： In a threshold analysis method obtaining threshold voltages of all bits in a flash memory through single processing, fail bit map information is examined in order from a smaller voltage applied to the flash memory. As to a bit exhibiting a value, read from the flash memory, first mismatching a determination value, the threshold voltage is settled on the basis of a voltage applied when the bit fails in reading.
摘要翻译： 在通过单个处理获得闪存中的所有位的阈值电压的阈值分析方法中，从施加到闪速存储器的较小电压的顺序检查故障位图信息。 对于显示一个值的位，从闪速存储器中读出，首先使确定值不匹配，阈值电压基于读取位故障时施加的电压来确定。
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公开(公告)号：US06690189B2
公开(公告)日：2004-02-10
申请号：US09927404
申请日：2001-08-13
申请人： Hisaya Mori , Shinji Yamada , Teruhiko Funakura
发明人： Hisaya Mori , Shinji Yamada , Teruhiko Funakura
IPC分类号： G01R3102
CPC分类号： H03M1/1071 , H03M1/66
摘要： There are provided a test apparatus and method for testing a semiconductor integrated circuit which enables improvements in the ease of operation and convenience of a BOST device and shortening of a test time. Numeric codes are assigned to tests. A test apparatus is equipped with memory and an analysis section. A test requirement table—in which hardware requirements required for conducting a test are set on a per-numeric-code basis—is stored in the memory. Test requirements corresponding to a numeric code are read from the memory, whereupon a test is performed. The analysis section analyzes a digital test output and sends the result of analysis to an external controller.
摘要翻译： 提供了一种用于测试半导体集成电路的测试装置和方法，其能够改善BOST设备的操作的便利性和便利性，并缩短测试时间。 数字代码被分配给测试。 测试装置配备有记忆和分析部分。 测试要求表（其中进行测试所需的硬件要求以每数字代码为基础设置）存储在存储器中。 从存储器读取对应于数字代码的测试要求，然后进行测试。 分析部分分析数字测试输出，并将分析结果发送给外部控制器。
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公开(公告)号：US06587975B2
公开(公告)日：2003-07-01
申请号：US09346268
申请日：1999-07-01
申请人： Hisaya Mori , Teruhiko Funakura
发明人： Hisaya Mori , Teruhiko Funakura
IPC分类号： G11C2900
CPC分类号： G11C29/56 , G11C16/04 , G11C2029/5606
摘要： A semiconductor test apparatus and method for performing a test on a nonvolatile semiconductor memory such as a flash memory while preventing excessive erasing with reliability. In each erase operation, all addresses are scanned to fetch an error address and error data into a catch memory. Then, on the basis of error information (error address and error data), a rewrite operation is performed to write data on all memory cells. The write data varies according to a comparison result between an address signal and an error address signal. If they disagree, a “0” is written on a memory cell at the address. If they agree, a “0” is written on a “pass” memory cell and a “1” is virtually written on a fail memory cell.
摘要翻译： 一种用于在诸如闪存之类的非易失性半导体存储器上执行测试的半导体测试装置和方法，同时可靠地防止过度擦除。 在每个擦除操作中，扫描所有地址以将错误地址和错误数据提取到捕获存储器中。 然后，基于错误信息（错误地址和错误数据），执行重写操作以将数据写入所有存储器单元。 写入数据根据地址信号和错误地址信号之间的比较结果而变化。 如果它们不同意，则在地址上的存储单元上写入“0”。 如果它们同意，则在“通过”存储单元上写入“0”，并且虚拟地将“1”写入故障存储单元。
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