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公开(公告)号：US07372743B2
公开(公告)日：2008-05-13
申请号：US11639128
申请日：2006-12-13
申请人： Masaru Yano , Hideki Arakawa , Mototada Sakashita , Akira Ogawa , Yoshiaki Shinmura , Hajime Aoki
发明人： Masaru Yano , Hideki Arakawa , Mototada Sakashita , Akira Ogawa , Yoshiaki Shinmura , Hajime Aoki
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation, a charge accumulation operation is performed, as a preset operation in the initialization operation, on second trapping regions of first and second dynamic reference cells to a charge accumulation operation on a second trapping region of the memory cell. In addition, at the time of data rewrite, preprogram verification and preprogramming are performed on the first trapping regions. This makes it possible to shorten the time taken for initialization and data rewrite.
摘要翻译： 一种具有存储模式的非易失性存储装置的控制方法，其中根据在第一捕获区域中是否存在电荷而存储具有捕获电介质层1位数据的存储单元。 在动态参考单元初始化操作中，作为初始化操作中的预设操作，在第一和第二动态参考单元的第二陷印区域上执行电荷累积操作，以对存储单元的第二陷印区域进行电荷累积操作。 此外，在数据重写时，对第一捕获区域执行预编程验证和预编程。 这使得可以缩短初始化和数据重写所花费的时间。
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公开(公告)号：US20070183193A1
公开(公告)日：2007-08-09
申请号：US11639128
申请日：2006-12-13
申请人： Masaru Yano , Hideki Arakawa , Mototada Sakashita , Akira Ogawa , Yoshiaki Shinmura , Hajime Aoki
发明人： Masaru Yano , Hideki Arakawa , Mototada Sakashita , Akira Ogawa , Yoshiaki Shinmura , Hajime Aoki
CPC分类号： G11C16/0475
摘要： A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation, a charge accumulation operation is performed, as a preset operation in the initialization operation, on second trapping regions of first and second dynamic reference cells to a charge accumulation operation on a second trapping region of the memory cell. In addition, at the time of data rewrite, preprogram verification and preprogramming are performed on the first trapping regions. This makes it possible to shorten the time taken for initialization and data rewrite.
摘要翻译： 一种具有存储模式的非易失性存储装置的控制方法，其中根据在第一捕获区域中是否存在电荷而存储具有捕获电介质层1位数据的存储单元。 在动态参考单元初始化操作中，作为初始化操作中的预设操作，在第一和第二动态参考单元的第二陷印区域上执行电荷累积操作，以对存储单元的第二陷印区域进行电荷累积操作。 此外，在数据重写时，对第一捕获区域执行预编程验证和预编程。 这使得可以缩短初始化和数据重写所花费的时间。
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公开(公告)号：US07385844B2
公开(公告)日：2008-06-10
申请号：US11494872
申请日：2006-07-27
申请人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
发明人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0475 , G11C16/0491 , G11C2216/14
摘要： A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a WR sense amplifier block (second memory unit) that stores first divided data to be written into the first bit and second divided data to be written into the second bit, the first divided data being formed by dividing the data into predetermined units, the second divided data being formed by dividing the data into predetermined units; and a control circuit that writes the second divided data into the first bit of the memory cells of the memory cell array (step S28) after writing the first divided data into the second bit of the memory cells of the memory cell array (step S22).
摘要翻译： 半导体器件包括：存储单元阵列，其具有多个非易失性存储单元，每个非易失性存储单元在电荷存储层中的不同区域中具有第一位和第二位; 存储要写入存储单元阵列的数据的SRAM阵列（第一存储器单元）; WR读出放大器块（第二存储器单元），其将要写入第一位的第一划分数据和要写入第二位的第二划分数据存储，第一划分数据通过将数据划分为预定单位形成，第二划分数据 通过将数据划分为预定单位形成分割数据; 以及将第一划分数据写入存储单元阵列的存储单元的第二位之后，将第二划分数据写入存储单元阵列的存储单元的第一位（步骤S28）的控制电路（步骤S 22）。
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公开(公告)号：US07362620B2
公开(公告)日：2008-04-22
申请号：US11394491
申请日：2006-03-31
申请人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
发明人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
IPC分类号： G11C7/00
CPC分类号： G11C16/10
摘要： A semiconductor device (1) includes a non-volatile memory cell array (2), a write/read circuit (30) writing data into and reading data from the non-volatile memory cell array (2), a data input/output circuit (80), and a volatile memory cell array (40) including a first latch circuit (41) that is connected to the write/read circuit (30) and latches first data, and a second latch circuit (42) that is connected to the data input/output circuit (80) and latches second data. The device (1) may further include an inverter circuit (310) that inverts the first data in accordance with the number of bits to be actually written among the first data, and a control circuit (3) that causes the second data to be latched in the second latch circuit (42) while the first data is being written into the non-volatile memory cell array (2). This semiconductor device (1) has a shorter writing time and a smaller circuit area.
摘要翻译： 半导体器件（1）包括非易失性存储单元阵列（2），将数据写入非易失性存储单元阵列（2）中并从其读取数据的写/读电路（30），数据输入/输出电路 （80）和包括连接到写入/读取电路（30）并锁存第一数据的第一锁存电路（41）的易失性存储单元阵列（40）和第二锁存电路（42），其连接到 数据输入/输出电路（80）并锁存第二数据。 装置（1）还可以包括根据在第一数据中实际写入的比特数来反转第一数据的逆变器电路（310）和使第二数据被锁存的控制电路（3） 在第二锁存电路（42）中，第一数据被写入非易失性存储单元阵列（2）中。 该半导体器件（1）具有较短的写入时间和较小的电路面积。
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公开(公告)号：US20070025154A1
公开(公告)日：2007-02-01
申请号：US11494872
申请日：2006-07-27
申请人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
发明人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0475 , G11C16/0491 , G11C2216/14
摘要： A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a WR sense amplifier block (second memory unit) that stores first divided data to be written into the first bit and second divided data to be written into the second bit, the first divided data being formed by dividing the data into predetermined units, the second divided data being formed by dividing the data into predetermined units; and a control circuit that writes the second divided data into the first bit of the memory cells of the memory cell array (step S28) after writing the first divided data into the second bit of the memory cells of the memory cell array (step S22).
摘要翻译： 半导体器件包括：存储单元阵列，其具有多个非易失性存储单元，每个非易失性存储单元在电荷存储层中的不同区域中具有第一位和第二位; 存储要写入存储单元阵列的数据的SRAM阵列（第一存储器单元）; WR读出放大器块（第二存储单元），存储要写入第一位的第一划分数据和要写入第二位的第二划分数据，第一划分数据通过将数据划分为预定单位形成，第二划分数据 通过将数据划分为预定单位形成分割数据; 以及将第一划分数据写入存储单元阵列的存储单元的第二位之后，将第二划分数据写入存储单元阵列的存储单元的第一位（步骤S28）的控制电路（步骤S 22）。
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公开(公告)号：US20060245247A1
公开(公告)日：2006-11-02
申请号：US11394491
申请日：2006-03-31
申请人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
发明人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
IPC分类号： G11C14/00
CPC分类号： G11C16/10
摘要： A semiconductor device (1) includes a non-volatile memory cell array (2), a write/read circuit (30) writing data into and reading data from the non-volatile memory cell array (2), a data input/output circuit (80), and a volatile memory cell array (40) including a first latch circuit (41) that is connected to the write/read circuit (30) and latches first data, and a second latch circuit (42) that is connected to the data input/output circuit (80) and latches second data. The device (1) may further include an inverter circuit (310) that inverts the first data in accordance with the number of bits to be actually written among the first data, and a control circuit (3) that causes the second data to be latched in the second latch circuit (42) while the first data is being written into the non-volatile memory cell array (2). This semiconductor device (1) has a shorter writing time and a smaller circuit area.
摘要翻译： 半导体器件（1）包括非易失性存储单元阵列（2），将数据写入非易失性存储单元阵列（2）中并从其读取数据的写/读电路（30），数据输入/输出电路 （80）和包括连接到写入/读取电路（30）并锁存第一数据的第一锁存电路（41）的易失性存储单元阵列（40）和第二锁存电路（42），其连接到 数据输入/输出电路（80）并锁存第二数据。 装置（1）还可以包括根据在第一数据中实际写入的比特数来反转第一数据的逆变器电路（310）和使第二数据被锁存的控制电路（3） 在第二锁存电路（42）中，第一数据被写入非易失性存储单元阵列（2）中。 该半导体器件（1）具有较短的写入时间和较小的电路面积。
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公开(公告)号：US20090109757A1
公开(公告)日：2009-04-30
申请号：US12275121
申请日：2008-11-20
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.
摘要翻译： 本发明提供一种半导体器件，其包括：包括非易失性存储单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。 在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。 本发明还提供一种控制半导体器件的方法。
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公开(公告)号：US08018767B2
公开(公告)日：2011-09-13
申请号：US12275121
申请日：2008-11-20
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.
摘要翻译： 本发明提供一种半导体器件，其包括：包括非易失性存储单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。 在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。 本发明还提供一种控制半导体器件的方法。
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公开(公告)号：US07450419B2
公开(公告)日：2008-11-11
申请号：US11636111
申请日：2006-12-07
申请人： Mototada Sakashita , Masaru Yano , Akira Ogawa , Tsutomu Nakai
发明人： Mototada Sakashita , Masaru Yano , Akira Ogawa , Tsutomu Nakai
CPC分类号： G11C16/10 , G11C2207/2263
摘要： The present invention provides a semiconductor device and a method for controlling a semiconductor device having a memory cell array having a plurality of nonvolatile memory cells, the method including detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array, comparing the number of bits with a predetermined number of bits, inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits, and programming the inversion data into the memory cell array. The method further includes detecting the number of bits to be written as next division data and comparing the number of bits of next division data with the predetermined number of bits, while concurrently programming the inversion data into the memory cell array.
摘要翻译： 本发明提供一种用于控制具有多个非易失性存储单元的存储单元阵列的半导体器件的半导体器件和方法，该方法包括检测要写入的位数，作为从要编程的数据划分的划分数据 进入存储单元阵列，将比特数与预定比特数进行比较，根据比特数与预定比特数比较的结果，反转或不反相除数数据以产生反转数据，并对 反转数据进入存储单元阵列。 该方法还包括检测要写入的比特数作为下一个分割数据，并将下一个分割数据的比特数与预定比特数进行比较，同时将反演数据编程到存储单元阵列中。
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公开(公告)号：US20070183211A1
公开(公告)日：2007-08-09
申请号：US11637260
申请日：2006-12-11
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.
摘要翻译： 本发明提供一种半导体器件，其包括：包括非易失性存储单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。 在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。 本发明还提供一种控制半导体器件的方法。
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