公开(公告)号：US5475692A

公开(公告)日：1995-12-12

申请号：US407986

申请日：1995-03-22

申请人： Susumu Hatano ,  Jun Kitano ,  Kenji Nishimoto ,  Shin'ichi Ikenaga ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Takeshi Wada ,  Michihiro Mishima ,  Fujio Yamamoto

发明人： Susumu Hatano ,  Jun Kitano ,  Kenji Nishimoto ,  Shin'ichi Ikenaga ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Takeshi Wada ,  Michihiro Mishima ,  Fujio Yamamoto

IPC分类号： G11C29/10 ,  G11C29/14 ,  G11C29/40 ,  G06F11/00

CPC分类号： G11C29/40 ,  G11C29/10 ,  G11C29/14

摘要： Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.

摘要翻译： 这里公开了一种半导体集成电路，用于测试所有位的两种非反相和反相状态的测试数据，其中一种预期数据可以压缩并输出测试结果。 半导体集成电路包括：决定电路25，用于决定第一状态，其中由模式寄存器锁存的预期数据和存储单元阵列的读取数据一致;第二状态，读取数据与 逻辑反转的预期数据的数据，以及通过异或门以外的第一状态和第二状态的第三状态，以产生能够区分各个状态的2位的信号。 这些状态根据高低电平和高阻抗通知到半导体集成电路的外部。

公开(公告)号：US06252299B1

公开(公告)日：2001-06-26

申请号：US09161725

申请日：1998-09-29

申请人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

发明人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

IPC分类号： H01L2328

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399

摘要： A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

摘要翻译： 一种半导体器件，包括树脂模具，位于树脂模具内部的两个半导体芯片，具有形成在前表面上的前后表面和外部端子以及从树脂模具的内部延伸到外部的引线，其中每个所述引线 至少在树脂模具中分支成两个分支引线，一个分支引线固定到一个半导体芯片的表面，并通过导线与表面上的外部端子电连接，另一个分支引线被固定到 另一个半导体芯片的表面，并通过导线与表面上的外部端子电连接，并且两个半导体芯片彼此堆叠，并且它们的背面彼此相对。

公开(公告)号：US20050094433A1

公开(公告)日：2005-05-05

申请号：US11002247

申请日：2004-12-03

申请人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

发明人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  G11C11/00

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399

摘要： A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

摘要翻译： 一种半导体器件，包括树脂模具，位于树脂模具内部的两个半导体芯片，具有形成在前表面上的前后表面和外部端子以及从树脂模具的内部延伸到外部的引线，其中每个所述引线 至少在树脂模具中分支成两个分支引线，一个分支引线固定到一个半导体芯片的表面，并通过导线与表面上的外部端子电连接，另一个分支引线被固定到 另一个半导体芯片的表面，并通过导线与表面上的外部端子电连接，并且两个半导体芯片彼此堆叠，并且它们的背面彼此相对。

公开(公告)号：US06426560B1

公开(公告)日：2002-07-30

申请号：US09608149

申请日：2000-06-30

申请人： Masayasu Kawamura ,  Atsushi Nakamura ,  Yoshihiro Sakaguchi ,  Yoshitaka Kinoshita ,  Yasushi Takahashi ,  Yoshihiko Inoue

发明人： Masayasu Kawamura ,  Atsushi Nakamura ,  Yoshihiro Sakaguchi ,  Yoshitaka Kinoshita ,  Yasushi Takahashi ,  Yoshihiko Inoue

IPC分类号： H01L27108

CPC分类号： H01L23/49537 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

摘要翻译： 以2位为单位进行存储器访问的两个存储器芯片通过将它们的背面放置在另一个上而被组装成堆叠结构，以便以4位单元进行存储器访问。 存储器模块被构造成使得多个这样的半导体存储器件，其中每个存储器芯片每个以2位单元进行存储器访问，通过将它们的背面放置在另一个上而被组装成堆叠结构，因此 为了以4位单位进行存储器访问，安装在正方形的安装电路板上，并且沿其一个区域形成有电极。

公开(公告)号：US07012321B2

公开(公告)日：2006-03-14

申请号：US10377713

申请日：2003-03-04

申请人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

发明人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

IPC分类号： H01L23/495 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01R43/00

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399

摘要： A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

公开(公告)号：US20050184380A1

公开(公告)日：2005-08-25

申请号：US11114175

申请日：2005-04-26

申请人： Kazuki Sakuma ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano

发明人： Kazuki Sakuma ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano

IPC分类号： G11C8/00 ,  H01L23/02 ,  H01L23/495

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.

公开(公告)号：US06566760B1

公开(公告)日：2003-05-20

申请号：US09666063

申请日：2000-09-19

申请人： Masayasu Kawamura ,  Atsushi Nakamura ,  Yoshihiro Sakaguchi ,  Yoshitaka Kinoshita ,  Yasushi Takahashi ,  Yoshihiko Inoue

发明人： Masayasu Kawamura ,  Atsushi Nakamura ,  Yoshihiro Sakaguchi ,  Yoshitaka Kinoshita ,  Yasushi Takahashi ,  Yoshihiko Inoue

IPC分类号： H01L2302

CPC分类号： H01L23/49537 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

公开(公告)号：US07227251B2

公开(公告)日：2007-06-05

申请号：US11114175

申请日：2005-04-26

申请人： Kazuki Sakuma ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano

发明人： Kazuki Sakuma ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano

IPC分类号： H01L23/02 ,  H01L23/48 ,  G11C8/00

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.

摘要翻译： 半导体器件通过层叠两个半导体芯片与其背面面对面设置而形成。 每个半导体芯片设置有用于时钟使能的外部引线，时钟使能信号和芯片选择信号被单独地输入。 在访问一个半导体芯片的情况下，通过将时钟使能信号和芯片选择信号设置为非活动状态，将另一个半导体芯片设置为低功耗模式。

公开(公告)号：US07122883B2

公开(公告)日：2006-10-17

申请号：US11002247

申请日：2004-12-03

申请人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

发明人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399

摘要： A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

公开(公告)号：US06885092B1

公开(公告)日：2005-04-26

申请号：US09453171

申请日：1999-12-02

申请人： Kazuki Sakuma ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano

发明人： Kazuki Sakuma ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano

IPC分类号： G11C8/00 ,  H01L23/02 ,  H01L23/495 ,  H01L23/28 ,  H01L23/04 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.

摘要翻译： 半导体器件通过层叠两个半导体芯片与其背面面对面设置而形成。 每个半导体芯片设置有用于时钟使能的外部引线，时钟使能信号和芯片选择信号被单独地输入。 在访问一个半导体芯片的情况下，通过将时钟使能信号和芯片选择信号设置为非活动状态，将另一个半导体芯片设置为低功耗模式。