公开(公告)号：US5576709A

公开(公告)日：1996-11-19

申请号：US267477

申请日：1994-06-28

申请人： Masato Onaya ,  Tsutomu Ishikawa

发明人： Masato Onaya ,  Tsutomu Ishikawa

IPC分类号： G11C7/00 ,  G11C7/16 ,  G11C27/02 ,  H03M1/00

CPC分类号： G11C7/16

摘要： An adder 22, a quantizer 20, and a variable integrator 24 execute A/D conversion and the result is stored in a memory 12. A time constant of the variable integrator at this time is controlled by a time constant controller 25. On the other hand, data from the memory is integrated by a variable integrator 28 to provide an analog signal. At this time, control data of the time constant controller 25 is transferred via a memory 32 to a time constant controller 33, which then uses the transferred control data to control the time constant of the variable integrator 28. When a mode is changed, switches 34 and 35 are turned off. Therefore, a signal with no input can be written into the memory 12 for initializing the memory 12.

摘要翻译： 加法器22，量化器20和可变积分器24执行A / D转换，并将结果存储在存储器12中。此时可变积分器的时间常数由时间常数控制器25控制。另一方面 通过可变积分器28将来自存储器的数据进行积分以提供模拟信号。 此时，时间常数控制器25的控制数据经由存储器32传送到时间常数控制器33，时间常数控制器33然后使用传送的控制数据来控制可变积分器28的时间常数。当模式改变时，开关 34和35关闭。 因此，无需输入的信号就可以被写入到用于初始化存储器12的存储器12中。

公开(公告)号：US5165099A

公开(公告)日：1992-11-17

申请号：US721864

申请日：1991-06-26

申请人： Masato Onaya ,  Tsutomu Ishikawa ,  Susumu Yamada

发明人： Masato Onaya ,  Tsutomu Ishikawa ,  Susumu Yamada

IPC分类号： H04S7/00

CPC分类号： H04S7/00 ,  H04S7/302

摘要： The balance of the volumes in right and left channels in a stereo play back system is controlled. The amount of attenuation of an attenuator provided in each channel is controlled. When the levels of right and left stereo signals are judged to be approximately the same, an oscillator is permitted to oscillate and the pulses from the oscillator are counted by a counter. In accordance with a voltage signal which corresponds to the level ratio of the right and left stereo signals, whether the counter must count upwards or downwards is determined. The balance is controlled in accordance with the amount of attenuation of each attenuator which is determined in accordance with the decoded count value. The completion of the control is detected when the level ratio of the right and left stereo signals alternately change after they become substantially equal, and the control is automatically finished. When the control is finished, the counter is reset so as to facilitate balance control when the source of the stereo signals is changed.

公开(公告)号：US5500825A

公开(公告)日：1996-03-19

申请号：US268165

申请日：1994-06-28

申请人： Masato Onaya ,  Susumu Yamada

发明人： Masato Onaya ,  Susumu Yamada

IPC分类号： G06F12/06 ,  G11C7/16 ,  G11C8/04 ,  G11C8/12 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/16 ,  G11C8/04 ,  G11C2207/16

摘要： A plurality of delay time data can easily be obtained. A data input unit 32 successively writes data into a memory 30. A data output unit 36 outputs data from six areas a-f in the memory 30 in the parallel manner. Selection units SW1 and SW2 successively select and output data read out from the six areas a-f in the memory 30. Locations to be read are shifted from one another by the selection units SW1 and SW2 to output data from different memory locations. Thus, a plurality of data which are different in time between write and readout operations (i.e., different delay times) can be obtained simultaneously.

摘要翻译： 可以容易地获得多个延迟时间数据。 数据输入单元32将数据连续地写入存储器30.数据输出单元36以并行方式从存储器30中的六个区域a-f输出数据。 选择单元SW1和SW2连续选择并输出从存储器30中的六个区域a-f读出的数据。要被读取的位置由选择单元SW1和SW2彼此移位，以从不同的存储器位置输出数据。 因此，可以同时获得写入和读出操作之间的时间不同的多个数据（即不同的延迟时间）。

公开(公告)号：US5073733A

公开(公告)日：1991-12-17

申请号：US510702

申请日：1990-04-18

申请人： Masaya Tanno ,  Masato Onaya

发明人： Masaya Tanno ,  Masato Onaya

IPC分类号： H03H17/08 ,  H03H17/00 ,  H03K5/00 ,  H03K5/135

CPC分类号： H03K5/135 ,  H03K2005/00247 ,  H03K2005/0026 ,  H03K2005/00267 ,  H03K2005/00273

摘要： A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter. A control signal for returning the counter in the initial value is generated by a first signal generating circuit when the end value is reached and a setting completion signal is generated by a second signal generating circuit when a setting of the further initial value is completed, and in response to both the signals, a muting signal is generated by a muting signal generating circuit, whereby the buffer amplifier mutes the output signal in response to the muting signal to prevent a noise due to random data from occurring at the output terminal.

公开(公告)号：US07268615B2

公开(公告)日：2007-09-11

申请号：US11270394

申请日：2005-11-09

申请人： Hiroshi Matsui ,  Masato Onaya

发明人： Hiroshi Matsui ,  Masato Onaya

IPC分类号： H03K5/00

CPC分类号： H04N9/78 ,  H03H19/004

摘要： A trap filter comprises a delay circuit made up of switched capacitors for delaying an input signal and outputting a delay signal, and an adding circuit for adding the input signal and the delay signal.

摘要翻译： 陷波滤波器包括由用于延迟输入信号并输出​​延迟信号的开关电容器构成的延迟电路，以及用于将输入信号和延迟信号相加的加法电路。

公开(公告)号：US20070076124A1

公开(公告)日：2007-04-05

申请号：US11470929

申请日：2006-09-07

申请人： Shunsuke Serizawa ,  Tetsuo Sakata ,  Masato Onaya

发明人： Shunsuke Serizawa ,  Tetsuo Sakata ,  Masato Onaya

IPC分类号： H03H11/26 ,  H04N5/14

CPC分类号： H03H19/004 ,  H04N11/165 ,  H04N11/186

摘要： A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors and which is charged/discharged by turning on/off gates of the charging and the discharging MOS transistors, and wherein the plurality of switched capacitor units are connected such that the input signal is input in common to each of drains of the charging MOS transistors and such that the capacitive elements are charged as well as such that the capacitive elements are discharged to allow the output signal to be output from each of drains of the discharging MOS transistors; and a switching control unit that performs on/off control of each of gates of the charging and the discharging MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence, wherein with respect to the two adjacent switched capacitor units of the plurality of switched capacitor units, the respective charging MOS transistors are adjacent to each other and the respective discharging MOS transistors are adjacent to each other, and drains of the respective charging MOS transistors are common and drains of the respective discharging MOS transistors are common.

摘要翻译： 获取从输入信号延迟的输出信号的延迟电路，包括：开关电容器组，其包括多个开关电容器单元，其中所述多个开关电容器单元中的每一个具有充电MOS晶体管和放电MOS晶体管，以及 电容元件，其连接到充电和放电MOS晶体管的源极，并且通过接通/关闭充电和放电MOS晶体管的栅极进行充电/放电，并且其中所述多个开关电容器单元被连接，使得输入 信号被共同地输入到充电MOS晶体管的每个漏极，并且使得电容元件被充电以及使得电容元件被放电以允许输出信号从放电MOS晶体管的每个漏极输出; 以及开关控制单元，其执行充电和放电MOS晶体管的每个栅极的导通/关断控制，以使得每个电容元件基于输入信号依次充电，并且在使每个 基于输入信号依次充电的电容元件使得最后一次充电的电容元件被放电，以允许输出信号依次输出，其中相对于多个的两个相邻的开关电容器单元 开关电容器单元，各个充电MOS晶体管彼此相邻并且各个放电MOS晶体管彼此相邻，并且各个充电MOS晶体管的漏极是共同的，并且各个放电MOS晶体管的漏极是共同的。

公开(公告)号：US20060179094A1

公开(公告)日：2006-08-10

申请号：US10534775

申请日：2003-11-14

申请人： Masato Onaya ,  Haruo Tamaki ,  Akira Iketani

发明人： Masato Onaya ,  Haruo Tamaki ,  Akira Iketani

IPC分类号： G06F7/58

CPC分类号： G06F7/588 ,  G06F7/584

摘要： A random number generator comprising a plurality of pseudo random number generating units that can respectively output random numbers in specified pseudo random number systems, an output random number generating unit that generates output random numbers based on outputs from a plurality of pseudo random number generating units, a physical random number generator that generates physical random numbers, and a switching unit for switching between the necessity and the non-necessity of updating output values from pseudo random number generating units based on physical random numbers generated by the physical random number generator. Based on which pseudo random number system an output random number is generated is randomly switched based on a physical random number, making it very difficult to predict a random number compared with a conventional one.

摘要翻译： 一种随机数发生器，包括可以在指定的伪随机数系统中分别输出随机数的多个伪随机数生成单元，输出随机数生成单元，其基于来自多个伪随机数生成单元的输出生成输出随机数， 产生物理随机数的物理随机数发生器，以及用于根据由物理随机数发生器产生的物理随机数，在从伪随机数生成单元更新输出值的必要性和不必要之间进行切换的切换单元。 基于哪个伪随机数系统，基于物理随机数随机地产生输出随机数，使得与常规随机数相比较难以预测随机数。

公开(公告)号：US07808857B2

公开(公告)日：2010-10-05

申请号：US11861437

申请日：2007-09-26

申请人： Masato Onaya ,  Shunsuke Serizawa

发明人： Masato Onaya ,  Shunsuke Serizawa

IPC分类号： G11C8/00

CPC分类号： G11C27/04 ,  G11C27/026

摘要： According to a preferred embodiment of the present invention, an analog memory includes a first to third memory blocks. Each of the first to third memory blocks includes a plurality of capacitive elements for storing electric charges corresponding to an input signal, an output line for transferring the electric charges, and a plurality of MOS transistors each for changing connection between the capacitive element and the output line. When a signal is outputted from the output line to a buffer circuit by sequentially connecting the capacitive element to the output line in the first memory block, all connections between the capacitive elements and the output line are disconnected in the second and third memory blocks with the output line of the first memory block and the output line of the second memory block connected.

摘要翻译： 根据本发明的优选实施例，模拟存储器包括第一至第三存储器块。 第一至第三存储块中的每一个包括用于存储对应于输入信号的电荷的多个电容元件，用于传送电荷的输出线，以及用于改变电容元件和输出之间的连接的多个MOS晶体管 线。 当通过将电容元件顺序地连接到第一存储块中的输出线将信号从输出线输出到缓冲电路时，电容元件和输出线之间的所有连接在第二和第三存储器块中被断开， 第一存储器块的输出线和第二存储器块的输出线相连。

公开(公告)号：US07800696B2

公开(公告)日：2010-09-21

申请号：US11470929

申请日：2006-09-07

申请人： Shunsuke Serizawa ,  Tetsuo Sakata ,  Masato Onaya

发明人： Shunsuke Serizawa ,  Tetsuo Sakata ,  Masato Onaya

IPC分类号： H04N9/66 ,  H03H11/26

CPC分类号： H03H19/004 ,  H04N11/165 ,  H04N11/186

摘要： A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors; and a switching control unit that performs on/off control of the charging and the discharging of the MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence.

摘要翻译： 获取从输入信号延迟的输出信号的延迟电路，包括：开关电容器组，其包括多个开关电容器单元，其中所述多个开关电容器单元中的每一个具有充电MOS晶体管和放电MOS晶体管，以及 连接到充电和放电MOS晶体管的源极的电容元件; 以及开关控制单元，其执行MOS晶体管的充电和放电的导通/关断控制，以使得每个电容元件基于输入信号依次充电，并且在使每个电容元件 基于输入信号依次充电的元件使上次充电的电容元件放电，以使输出信号依次输出。

公开(公告)号：US20060139496A1

公开(公告)日：2006-06-29

申请号：US11315982

申请日：2005-12-22

申请人： Hiroshi Matsui ,  Masato Onaya

发明人： Hiroshi Matsui ,  Masato Onaya

IPC分类号： H04N9/77 ,  H04N9/70 ,  H04N5/21

CPC分类号： H04N9/78

摘要： A video signal processing apparatus receives a video signal containing at least a luminance signal and a color difference signal. A trap filter attenuates a frequency band of the color difference signal to separate the luminance signal from the video signal. A bandpass filter attenuates a frequency band of the luminance signal to separate the color difference signal from the video signal. The trap filter is constituted by a switched capacitor filter that outputs the luminance signal with a delay time equivalent to a time difference between a delay time of the processing performed in a succeeding luminance signal processing circuit and a delay time of the processing performed in a color difference signal processing circuit. With this arrangement, the circuit scale of a filter circuit can be reduced and frequency characteristics of the filter can be stabilized.

摘要翻译： 视频信号处理装置接收至少包含亮度信号和色差信号的视频信号。 陷波滤波器衰减色差信号的频带，以将亮度信号与视频信号分离。 带通滤波器衰减亮度信号的频带以将色差信号与视频信号分离。 陷波滤波器由开关电容滤波器构成，该开关电容滤波器输出亮度信号，其延迟时间等于在后续亮度信号处理电路中执行的处理的延迟时间与以颜色执行的处理的延迟时间之间的时间差 差分信号处理电路。 利用这种布置，可以降低滤波电路的电路规模，并且可以使滤波器的频率特性稳定。