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    System LSI having a substrate-bias generation circuit with a substrate-bias control-value storage unit
    2.
    发明授权
    System LSI having a substrate-bias generation circuit with a substrate-bias control-value storage unit 失效
    具有具有衬底偏置控制值存储单元的衬底偏置产生电路的系统LSI

    公开(公告)号：US06654305B2

    公开(公告)日：2003-11-25

    申请号：US10259777

    申请日：2002-09-30

    申请人： Takanobu Tsunoda ,  Osamu Nishii

    发明人： Takanobu Tsunoda ,  Osamu Nishii

    IPC分类号： G11C700

    CPC分类号： G11C5/146

    摘要： A system LSI including substrate-bias generation circuits for supplying substrate biases independent of each other to functional modules integrated in the system LSI, a substrate-bias control circuit for controlling the substrate-bias generation circuits and a substrate-bias control-value storage unit for storing control values to be supplied to the substrate-bias generation circuits. The control values stored in the substrate-bias control-value storage unit are set by carrying out a predetermined operation. As a result, it is possible to provide a device for implementing both a high-speed operation and low power consumption without lowering the yield and for finely controlling the power consumption during the operation.

    摘要翻译： 一种系统LSI，包括用于将集成在系统LSI中的功能模块彼此独立地提供衬底偏压的衬底偏置生成电路，用于控制衬底偏置生成电路的衬底偏置控制电路和衬底偏置控制值存储单元 用于存储要提供给衬底偏置发生电路的控制值。 通过执行预定的操作来设定存储在基板偏置控制值存储单元中的控制值。 结果，可以提供一种用于实现高速操作和低功耗的装置，而不降低产量并精细地控制操作期间的功率消耗。

    Data processor and data processing system
    4.
    发明授权
    Data processor and data processing system 失效
    数据处理器和数据处理系统

    公开(公告)号：US5918045A

    公开(公告)日：1999-06-29

    申请号：US953387

    申请日：1997-10-17

    申请人： Osamu Nishii ,  Sadaki Nakano ,  Norio Nakagawa ,  Takanobu Tsunoda

    发明人： Osamu Nishii ,  Sadaki Nakano ,  Norio Nakagawa ,  Takanobu Tsunoda

    IPC分类号： G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/30072 ,  G06F9/324 ,  G06F9/3804 ,  G06F9/3842

    摘要： The data processor includes a CPU and an instruction prefetch buffer that prefetches an instruction executed by the CPU and stores it therein. The CPU contains a detection circuit for detecting whether or not a displacement from a branch instruction to a branch target instruction is a specific displacement on the basis of branch displacement information that the concerned branch instruction holds. The instruction prefetch buffer clears an instruction already prefetched when the detection circuit detects that the displacement is not the specific displacement and outputs a branch target instruction newly fetched to the CPU, and outputs a branch target instruction already prefetched to the CPU when the detection circuit detects that the displacement is the specific displacement. Thus, the date processor fetches a branch target instruction within a certain range from the instruction prefetch buffer at a high speed without adding the nullifying bit on the instruction code.

    摘要翻译： 数据处理器包括CPU和预取由CPU执行的指令并将其存储在其中的指令预取缓冲器。 CPU包含检测电路，用于根据相关分支指令保持的分支位移信息来检测从分支指令到分支目标指令的位移是否是特定位移。 当检测电路检测到位移不是特定位移时，指令预取缓冲器清除已经预取的指令，并将新提取的分支目标指令输出到CPU，并且当检测电路检测到时，将已经预取的分支目标指令输出到CPU 位移是具体的位移。 因此，日期处理器从指令预取缓冲器中以高速度在一定范围内提取分支目标指令，而不在指令代码上添加无效位。

    Low power consumption microprocessor
    6.
    发明申请
    Low power consumption microprocessor 有权
    低功耗微处理器

    公开(公告)号：US20050169086A1

    公开(公告)日：2005-08-04

    申请号：US11095685

    申请日：2005-04-01

    申请人： Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

    发明人： Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

    IPC分类号： G06F9/38 ,  G06F1/32 ,  G06F7/00 ,  G06F9/318 ,  G06F9/45 ,  G11C7/00

    CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F8/4432 ,  G06F9/30083 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3017 ,  G06F9/3877 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/41

    摘要： A microprocessor including a first cache memory, a first instruction fetch unit coupled to the first cache memory, a first instruction decoder coupled to the first instruction fetch unit, and a first processing unit coupled to the first instruction decoder, wherein, when the first instruction fetch unit is inputted with a first instruction which is performed by the first processing unit, the first instruction fetch unit outputs the first instruction to the first instruction decoder, wherein when the first instruction fetch unit is inputted with a second instruction which is not performed by the first processing unit, the first instruction fetch unit outputs a specific instruction to the first instruction decoder, and wherein, in the case where the first instruction fetch unit outputs the specific instruction to the first instruction decoder, the supply of clock pulse to the first processing unit is halted.

    摘要翻译： 包括第一高速缓冲存储器，耦合到第一高速缓存存储器的第一指令提取单元，耦合到第一指令提取单元的第一指令解码器和耦合到第一指令解码器的第一处理单元的微处理器，其中当第一指令 输入第一指令的第一指令由第一处理单元输入，第一指令提取单元向第一指令解码器输出第一指令，其中当第一指令提取单元输入第二指令时，第二指令不由第一指令执行， 第一处理单元，第一指令获取单元向第一指令解码器输出特定指令，并且其中，在第一指令提取单元向第一指令解码器输出特定指令的情况下，向第一指令解码器提供时钟脉冲 处理单元停止。

    Data processing system with branch target addressing using upper and lower bit permutation
    8.
    发明授权
    Data processing system with branch target addressing using upper and lower bit permutation 失效
    具有分支目标寻址的数据处理系统使用高位和低位置换

    公开(公告)号：US08145889B2

    公开(公告)日：2012-03-27

    申请号：US12912836

    申请日：2010-10-27

    申请人： Osamu Nishii

    发明人： Osamu Nishii

    IPC分类号： G06F9/00

    CPC分类号： G06F9/322 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3806

    摘要： A data processor or a data processing system used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. A multiple with which the displacement is multiplied can be changed in accordance with the mode.

    摘要翻译： 在兼容模式下使用的数据处理器或数据处理系统，其中指定逻辑地址空间的地址的位数在通过分支指令的位移的扩展引用分支地址表时变化。 在生成第一分支指令的分支地址时，数据处理器或数据处理系统根据指定逻辑地址空间的地址的位数来优化与该位移相乘的倍数，将扩展地址 信息到寄存器的值，并且是指通过添加获得的具有地址信息的分支地址表。 所引用的信息用作分支地址。 可以根据该模式来改变与该位移相乘的倍数。

    Data processing system to calculate indexes into a branch target address table based on a current operating mode
    9.
    发明授权
    Data processing system to calculate indexes into a branch target address table based on a current operating mode 失效
    数据处理系统根据当前的运行模式计算索引到分支目标地址表中

    公开(公告)号：US07836286B2

    公开(公告)日：2010-11-16

    申请号：US12013468

    申请日：2008-01-13

    申请人： Osamu Nishii

    发明人： Osamu Nishii

    IPC分类号： G06F9/44

    CPC分类号： G06F9/322 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3806

    摘要： The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.

    摘要翻译： 本发明提供一种数据处理器或数据处理系统，其可以在兼容模式中使用，其中指定逻辑地址空间的地址的位数在通过扩展a的扩展引用分支地址表时变化 分支指令。 在生成第一分支指令的分支地址时，数据处理器或数据处理系统根据指定逻辑地址空间的地址的位数来优化与该位移相乘的倍数，将扩展地址 信息到寄存器的值，并且是指通过添加获得的具有地址信息的分支地址表。 所引用的信息用作分支地址。 为了适应于使用指定逻辑地址空间的地址的不同位数的兼容模式，根据该模式来改变与该位移相乘的倍数就足够了。

    Memory system performing fast access to a memory location by omitting the transfer of a redundant address
    10.
    再颁专利
    Memory system performing fast access to a memory location by omitting the transfer of a redundant address 有权
    存储器系统通过省略冗余地址的传输来执行对存储器位置的快速访问

    公开(公告)号：USRE41589E1

    公开(公告)日：2010-08-24

    申请号：US10290367

    申请日：2002-11-08

    申请人： Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

    发明人： Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0215 ,  G06F13/1631

    摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

    摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。