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公开(公告)号：US07932901B2
公开(公告)日：2011-04-26
申请号：US11880699
申请日：2007-07-24
IPC分类号： G09G5/00
CPC分类号： G06F1/3203 , G06F1/324 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/08 , G09G2310/0267 , G09G2310/027 , G09G2330/021 , Y02D10/126
摘要： A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.
摘要翻译： 具有低功耗和小布局区域的定时发生电路，包括作为一个外围驱动电路的定时发生电路的显示装置和包括作为显示输出部分的显示装置的便携式终端。 在形成在绝缘基板上的定时发生电路中，基于主时钟MCK产生具有不同频率的输出脉冲SRFF1out〜SRFFnout，时钟发生电路（11）生成频率低于主时钟MCK的工作时钟 频率。 然后，基于该工作时钟，计数部（12）工作，从移位寄存器（121-1）至（121-m）依次输出移位脉冲S / R1out至S / Rmount。 输出脉冲生成部（13）根据移位脉冲S / R1out〜S / Rmount的组合，生成输出脉冲SF1out〜SFnout。
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2.发明申请Liquid crystal display device, method of controlling the same, and mobile terminal 有权液晶显示装置，其控制方法和移动终端公开(公告)号：US20070195038A1
公开(公告)日：2007-08-23
申请号：US11789279
申请日：2007-04-23
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3655 , G09G3/3688 , G09G2300/0876 , G09G2310/0245 , G09G2310/027 , G09G2310/06 , G09G2310/063 , G09G2320/0204 , G09G2320/0219 , G09G2320/0257 , G09G2330/026 , G09G2330/027
摘要： A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side. This allows the screen to turn white in a normally white type liquid crystal display, and to turn black in a normally black type liquid crystal display. Image distortion at power on/off time can thus be prevented.
摘要翻译： 一种液晶显示装置，其能够与整个系统相关联地减小尺寸和成本，开始显示在通电时间没有图像失真的图像，并且在断电时关闭屏幕而不进行图像保持;控制方法 液晶显示装置和结合有液晶显示装置的移动终端作为画面显示。 在设置有显示单元（12）的玻璃基板（11）上，诸如接口电路（13），定时发生器（14），参考电压驱动器（15），CS驱动器（18）， 设置VCOM驱动器（19）和电压调节电路（20）以及水平驱动器（16）和垂直驱动器（17）。 当从外部源提供显示复位控制脉冲PCI时，将预定电压写入像素，同时将CS电压和VCOM电压调整到与像素电压相同的电平施加到共电极侧。 这允许屏幕在普通白色液晶显示器中变为白色，并且在常黑型液晶显示器中变黑。 因此可以防止电源开/关时的图像失真。
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3.发明授权Liquid crystal display device, method of controlling the same, and mobile terminal 有权液晶显示装置，其控制方法和移动终端公开(公告)号：US07864170B2
公开(公告)日：2011-01-04
申请号：US11789279
申请日：2007-04-23
IPC分类号： G06F3/038
CPC分类号： G09G3/3648 , G09G3/3655 , G09G3/3688 , G09G2300/0876 , G09G2310/0245 , G09G2310/027 , G09G2310/06 , G09G2310/063 , G09G2320/0204 , G09G2320/0219 , G09G2320/0257 , G09G2330/026 , G09G2330/027
摘要： A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side. This allows the screen to turn white in a normally white type liquid crystal display, and to turn black in a normally black type liquid crystal display. Image distortion at power on/off time can thus be prevented.
摘要翻译： 一种液晶显示装置，其能够与整个系统相关联地减小尺寸和成本，开始显示在通电时间没有图像失真的图像，并且在断电时关闭屏幕而不进行图像保持;控制方法 液晶显示装置和结合有液晶显示装置的移动终端作为画面显示。 在设置有显示单元（12）的玻璃基板（11）上，诸如接口电路（13），定时发生器（14），参考电压驱动器（15），CS驱动器（18）， 设置VCOM驱动器（19）和电压调节电路（20）以及水平驱动器（16）和垂直驱动器（17）。 当从外部源提供显示复位控制脉冲PCI时，将预定电压写入像素，同时将CS电压和VCOM电压调整到与像素电压相同的电平施加到共电极侧。 这允许屏幕在普通白色液晶显示器中变为白色，并且在常黑型液晶显示器中变黑。 因此可以防止电源开/关时的图像失真。
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公开(公告)号：US20070262975A1
公开(公告)日：2007-11-15
申请号：US11880699
申请日：2007-07-24
IPC分类号： G06F3/038
CPC分类号： G06F1/3203 , G06F1/324 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/08 , G09G2310/0267 , G09G2310/027 , G09G2330/021 , Y02D10/126
摘要： A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.
摘要翻译： 具有低功耗和小布局区域的定时发生电路，包括作为一个外围驱动电路的定时发生电路的显示装置和包括作为显示输出部分的显示装置的便携式终端。 在定时发生电路中，形成在绝缘衬底上并基于主时钟MCK产生具有不同频率的输出脉冲SRFF1至SRFFnout，时钟发生电路（11）产生频率低于主器件的工作时钟 时钟MCK频率。 然后，基于该工作时钟，计数部（12）进行动作，从移位寄存器（121-1）〜（121-m）依次输出移位脉冲S / R 1〜S / Rmount。 输出脉冲生成部（13）根据移位脉冲S / R 1 out〜S / R mount的组合，生成输出脉冲SF1〜SFnout。
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5.发明授权Logic circuit, timing generation circuit, display device, and portable terminal 有权逻辑电路，定时生成电路，显示装置和便携式终端公开(公告)号：US07126376B2
公开(公告)日：2006-10-24
申请号：US10485374
申请日：2003-05-30
IPC分类号： H03K19/173 , H03K3/037
CPC分类号： G09G3/20 , G09G3/3648 , G09G5/18 , G09G2300/0408 , G09G2310/0289 , G09G2310/08
摘要： When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.
摘要翻译： 当通过使用具有大的元件特性变化的晶体管形成缓冲器时，可能会发生输入时钟脉冲与复位脉冲之间的定时偏差。 当定时的偏差变大时，会发生故障，相对于元件特性的变化，操作余量变小。 在形成在绝缘基板上并具有两个TFF（12,13）的定时产生电路中，用于产生点时钟DCK和频率与输入外部的主时钟MCK同步的频率不同的水平时钟HCK 在相对于两个TFF（12,13）的脉冲发生电路15处产生分离的复位脉冲drst和hrst，并且在单独的定时执行复位操作。 因此，即使当通过使用具有大的元件特性变化的TFT和粗略的处理规则形成每个电路时，也可以确保大的操作余量。
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6.发明授权Digital-to-analog converter and display unit with such digital-to-analog converter 有权数模转换器和具有这种数模转换器的显示单元公开(公告)号：US06459395B1
公开(公告)日：2002-10-01
申请号：US09697726
申请日：2000-10-27
IPC分类号： H03M166
CPC分类号： G09G3/3696 , G09G3/3655 , G09G3/3688 , G09G2300/0408 , G09G2310/027 , H03M1/765
摘要： In a reference-voltage-selection-type D/A converter, the channel widths of transistors of MOS switches of gradation selecting units are weighted depending on the selected gradation. Specifically, the channel width of the MOS switches Qn11, Qn12 is represented by W0, the channel width of the MOS switches Qn13, Qp11 is represented by W1, the channel width of the MOS switches Qp12, Qn14 is represented by W2, and the channel width of the MOS switches Qp13, Qp14 is represented by W3. The channel width W3 is set to a size corresponding to the maximum capacitance of a column line, and the other channel widths W0, W1, W2 are set to satisfy the relationship: W0
摘要翻译： 在参考电压选择型D / A转换器中，灰度选择单元的MOS开关的晶体管的沟道宽度根据所选择的灰度进行加权。 具体地，MOS开关Qn11，Qn12的沟道宽度由W0表示，MOS开关Qn13，Qp11的沟道宽度由W1表示，MOS开关Qp12，Qn14的沟道宽度由W2表示，沟道 MOS开关Qp13，Qp14的宽度由W3表示。 通道宽度W3被设置为与列线的最大电容相对应的尺寸，并且另一个通道宽度W0，W1，W2被设置为满足关系：W0
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公开(公告)号：US07250941B2
公开(公告)日：2007-07-31
申请号：US10484994
申请日：2003-05-06
IPC分类号： G09G5/00
CPC分类号： G06F1/3203 , G06F1/324 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/08 , G09G2310/0267 , G09G2310/027 , G09G2330/021 , Y02D10/126
摘要： A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.
摘要翻译： 具有低功耗和小布局区域的定时发生电路，包括作为一个外围驱动电路的定时发生电路的显示装置和包括作为显示输出部分的显示装置的便携式终端。 在定时发生电路中，形成在绝缘衬底上并基于主时钟MCK产生具有不同频率的输出脉冲SRFF1至SRFFnout，时钟发生电路（11）产生频率低于主器件的工作时钟 时钟MCK频率。 然后，基于该工作时钟，计数部（12）进行动作，从移位寄存器（121-1）〜（121-m）依次输出移位脉冲S / R 1〜S / Rmount。 输出脉冲生成部（13）根据移位脉冲S / R 1 out〜S / R mount的组合，生成输出脉冲SF1〜SFnout。
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公开(公告)号：US07209132B2
公开(公告)日：2007-04-24
申请号：US10485280
申请日：2003-05-30
IPC分类号： G09G5/00
CPC分类号： G09G3/3648 , G09G3/3655 , G09G3/3688 , G09G2300/0876 , G09G2310/0245 , G09G2310/027 , G09G2310/06 , G09G2310/063 , G09G2320/0204 , G09G2320/0219 , G09G2320/0257 , G09G2330/026 , G09G2330/027
摘要： A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side. This allows the screen to turn white in a normally white type liquid crystal display, and to turn black in a normally black type liquid crystal display. Image distortion at power on/off time can thus be prevented.
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9.发明授权Logic circuit, timing generation circuit, display device, and portable terminal 有权逻辑电路，定时生成电路，显示装置和便携式终端公开(公告)号：US07368945B2
公开(公告)日：2008-05-06
申请号：US11441879
申请日：2006-05-26
IPC分类号： H03K19/173 , H03K3/037
CPC分类号： G09G3/20 , G09G3/3648 , G09G5/18 , G09G2300/0408 , G09G2310/0289 , G09G2310/08
摘要： When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.
摘要翻译： 当通过使用具有大的元件特性变化的晶体管形成缓冲器时，可能会发生输入时钟脉冲与复位脉冲之间的定时偏差。 当定时的偏差变大时，会发生故障，相对于元件特性的变化，操作余量变小。 在形成在绝缘基板上并具有两个TFF（12,13）的定时产生电路中，用于产生点时钟DCK和频率与输入外部的主时钟MCK同步的频率不同的水平时钟HCK 在相对于两个TFF（12,13）的脉冲发生电路15处产生分离的复位脉冲drst和hrst，并且在单独的定时执行复位操作。 因此，即使当通过使用具有大的元件特性变化的TFT和粗略的处理规则形成每个电路时，也可以确保大的操作余量。
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公开(公告)号：US20060214694A1
公开(公告)日：2006-09-28
申请号：US11441879
申请日：2006-05-26
IPC分类号： H03K19/00
CPC分类号： G09G3/20 , G09G3/3648 , G09G5/18 , G09G2300/0408 , G09G2310/0289 , G09G2310/08
摘要： When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.
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