公开(公告)号：US5150301A

公开(公告)日：1992-09-22

申请号：US545528

申请日：1990-06-29

申请人： Masuo Kashiwabara ,  Hideyuki Kojima ,  Hiromitsu Yamaura ,  Seiichi Otani

发明人： Masuo Kashiwabara ,  Hideyuki Kojima ,  Hiromitsu Yamaura ,  Seiichi Otani

IPC分类号： F02D41/02 ,  F02D41/14

CPC分类号： F02D41/2454 ,  F02D41/248 ,  F02D41/2416 ,  F02D41/2445

摘要： An air/fuel mixture ratio learning control system for an internal combustion engine using a mixed fuel employs a learnt correction coefficient which is used both in a FEEDBACK mode air/fuel ratio control and in an OPEN LOOP mode air/fuel ratio control. The learnt correction coefficient is derived based on a FEEDBACK air/fuel ratio dependent correction coefficient per one of preselected engine driving ranges and per one of preselected concentration ranges of one fuel component contained in the mixed fuel. The learnt correction coefficient is cyclically derived in a preselected stable engine driving condition during the FEEDBACK mode air/fuel ratio control for updating a previously derived and stored one to minimize a deviation of the FEEDBACK correction coefficient from a reference value. The control system performs the FEEDBACK mode air/fuel ratio control with the FEEDBACK correction coefficient and the learnt correction coefficient, while the control system performs the OPEN LOOP mode air/fuel ratio control with the learnt correction coefficient.

摘要翻译： 使用混合燃料的内燃机的空气/燃料混合比学习控制系统采用在反馈模式空气/燃料比控制和OPEN循环模式空燃比控制中使用的学习校正系数。 所学习的校正系数基于每个预选发动机驱动范围和混合燃料中包含的一种燃料成分的预选浓度范围中的每一个的反馈空燃比依赖校正系数而导出。 在用于更新先前导出和存储的反馈模式空气/燃料比控制中的预定稳定的发动机驱动条件下，所学习的校正系数被循环地导出，以使得反馈校正系数与参考值的偏差最小化。 控制系统利用FEEDBACK校正系数和学习校正系数进行FEEDBACK模式空燃比控制，而控制系统利用学习的校正系数执行OPEN LOOP模式空燃比控制。

公开(公告)号：US08158483B2

公开(公告)日：2012-04-17

申请号：US13075625

申请日：2011-03-30

申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823892 ,  H01L27/0629

摘要： A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.

摘要翻译： 半导体器件制造方法包括：在半导体衬底中形成具有1以上的纵横比的隔离区域，形成栅极绝缘膜，形成硅栅电极和硅电阻元件，在栅电极上形成侧壁间隔物， 用磷和第二有源区掺杂第一有源区，通过离子注入掺杂p型杂质的电阻元件，在500℃或更低的温度下形成自对准硅化物块，沉积覆盖自对准硅化物块的金属层，并选择性地形成金属硅化物 层。 该方法可以进一步包括：形成厚和薄的栅极绝缘膜，并且执行不穿透厚栅极绝缘膜的第一导电类型的离子的注入和相反导电类型的离子的倾斜注入也穿透厚栅极绝缘膜 在形成侧壁间隔物之前。

公开(公告)号：US20100136758A1

公开(公告)日：2010-06-03

申请号：US12627941

申请日：2009-11-30

申请人： Hiroyuki Ogawa ,  Hideyuki Kojima

发明人： Hiroyuki Ogawa ,  Hideyuki Kojima

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/10897 ,  H01L28/40

摘要： A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method includes forming an active region on a surface layer of a semiconductor substrate, forming a first word line extending in a first direction on the gate insulating film in the first memory cell array region, and forming a second word line extending in a second direction crossing the first direction on the gate insulating film in the second memory cell array region, wherein the ion implantation into the active region is performed from a direction that is inclined from a direction vertical to the surface of the semiconductor substrate and is oblique with respect to both the first direction and the second direction.

摘要翻译： 一种制造具有第一存储单元阵列区域和第二存储单元阵列区域的半导体器件的方法，所述方法包括在半导体衬底的表面层上形成有源区，形成在第一方向上延伸的第一字线 栅极绝缘膜，并且形成在第二存储单元阵列区域中的栅极绝缘膜上沿与第一方向交叉的第二方向延伸的第二字线，其中从有源区域的离子注入到 从与半导体衬底的表面垂直的方向倾斜并相对于第一方向和第二方向倾斜的方向。

公开(公告)号：US07605041B2

公开(公告)日：2009-10-20

申请号：US12000047

申请日：2007-12-07

申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

摘要： Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.

摘要翻译： 具有期望特性的多种晶体管以较少的工艺制造。 半导体器件包括到达第一深度的隔离区域，第一导电类型的第一和第二阱，形成在第一阱中并具有第一厚度的栅极绝缘膜的第一晶体管，以及形成在第二阱中的第二晶体管， 具有第二厚度小于第一厚度的栅极绝缘膜。 第一阱具有仅在等于或大于第一深度的深度处具有极值最大值的第一杂质浓度分布。 第二阱具有第二杂质浓度分布，其是第一杂质浓度分布的叠加，以及在比第一深度小的第二深度处显示极值最大值的另一杂质浓度分布，叠加还显示在 第二深度

公开(公告)号：US07592216B2

公开(公告)日：2009-09-22

申请号：US12127067

申请日：2008-05-27

申请人： Jun Lin ,  Hiroyuki Ogawa ,  Hideyuki Kojima

发明人： Jun Lin ,  Hiroyuki Ogawa ,  Hideyuki Kojima

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/40

摘要： A method of manufacturing a semiconductor device includes forming a first trench in a capacitor device region of a semiconductor substrate, forming a capacitor insulation film over a sidewall surface of the first trench, forming a semiconductor film to cover the first trench, a resistor device region of the semiconductor substrate and a logic device region of the semiconductor substrate, introducing a first impurity element into the semiconductor film formed over the first trench, patterning the semiconductor film to form a top electrode in the capacitor device region, a resistor in the resistor device region and a gate electrode in the logic device region, annealing the semiconductor substrate, and introducing a second impurity element in the resistor.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底的电容器器件区域中形成第一沟槽，在第一沟槽的侧壁表面上形成电容器绝缘膜，形成覆盖第一沟槽的半导体膜，电阻器器件区域 的半导体衬底和半导体衬底的逻辑器件区域，在第一沟槽上形成的半导体膜中引入第一杂质元素，对半导体膜进行构图以在电容器器件区域中形成顶电极，电阻器件中的电阻器 区域和逻辑器件区域中的栅电极，退火半导体衬底，并在电阻器中引入第二杂质元素。

公开(公告)号：US20080054362A1

公开(公告)日：2008-03-06

申请号：US11785793

申请日：2007-04-20

申请人： Hiroyuki Ogawa ,  Hideyuki Kojima ,  Taiji Ema

发明人： Hiroyuki Ogawa ,  Hideyuki Kojima ,  Taiji Ema

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548

摘要： The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode.

摘要翻译： 制造半导体器件的方法包括形成包括层叠结构的栅电极的晶体管的第一区域，形成包括单层结构的栅电极的晶体管的第二区域和位于 在第一区域和第二区域之间的边界部分中包括：沉积第一导电膜，使第一区域和第三区域中的第一导电膜图形化，使得外边缘位于第三区域中，沉积第二导电膜 膜，图案化第二导电膜，以在离开第二导电膜的同时在第一区域中形成控制栅极，覆盖第二区域并且使内边缘位于第一导电膜的外边缘的内侧，并且使第二导电膜 在第二区域中形成栅电极。

公开(公告)号：US20060119695A1

公开(公告)日：2006-06-08

申请号：US11271834

申请日：2005-11-14

申请人： Hideyuki Kojima

发明人： Hideyuki Kojima

IPC分类号： B41J2/385

CPC分类号： B41J11/007

摘要： In a transport belt drive control device, a first detection unit has a first resolution and indirectly detects a feed amount of a transport belt, a control unit controls drive of the transport belt based on an output of the first detection unit, and a second detection unit has a second, lower resolution and directly detects the feed amount of the transport belt. The control unit is configured to switch, when an output of the second detection unit is determined as not allowing detection of a stop position of the transport belt, the direct detection of the belt feed amount by the second detection unit to the indirect detection of the belt feed amount by the first detection unit, so that the drive of the transport belt is controlled based on the output of the first detection unit.

摘要翻译： 在传送带驱动控制装置中，第一检测单元具有第一分辨率并间接地检测传送带的进给量，控制单元基于第一检测单元的输出来控制传送带的驱动，第二检测 单元具有第二，较低的分辨率，并直接检测输送带的进给量。 控制单元被配置为当第二检测单元的输出被确定为不允许检测输送带的停止位置时，将第二检测单元的带进给量直接检测为间接检测 通过第一检测单元输送皮带进给量，从而基于第一检测单元的输出来控制传送带的驱动。

公开(公告)号：US20060017181A1

公开(公告)日：2006-01-26

申请号：US10988530

申请日：2004-11-16

申请人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

发明人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

IPC分类号： H01L31/109

CPC分类号： H01L27/1104 ,  G11C5/063 ,  G11C11/412 ,  H01L27/11 ,  Y10S257/903

摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.

公开(公告)号：US06567312B1

公开(公告)日：2003-05-20

申请号：US09689714

申请日：2000-10-13

申请人： Satoshi Torii ,  Hideyuki Kojima ,  Hiroshi Mawatari

发明人： Satoshi Torii ,  Hideyuki Kojima ,  Hiroshi Mawatari

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/3454

摘要： In a flash memory having, for example, a single-gate type memory cell consisting of the gate electrode provided via a thin charge trap layer on a semiconductor substrate, there is provided a non-volatile semiconductor memory that is characterized in applying a short pulse to the memory cell to partly remove the electrons from the charge trap layer after writing the data to the memory cell. This ensures the write operation reliability of non-volatile semiconductor memory such as single-gate type flash memory or the like without changing the basic structure of the memory cell array.

摘要翻译： 在具有例如由通过半导体衬底上的薄电荷陷阱层提供的栅极组成的单栅极型存储单元的闪存中，提供了一种非易失性半导体存储器，其特征在于施加短脉冲 在将数据写入到存储单元之后，将其从电荷陷阱层部分去除。 这确保了不改变存储单元阵列的基本结构的非易失性半导体存储器诸如单栅极型闪存等的写操作可靠性。

公开(公告)号：USD430900S

公开(公告)日：2000-09-12

申请号：US115244

申请日：1999-12-09

申请人： Shingo Iwata ,  Hideyuki Kojima ,  Toshiro Fujii ,  Yoshikazu Saito

设计人： Shingo Iwata ,  Hideyuki Kojima ,  Toshiro Fujii ,  Yoshikazu Saito